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Rabindra K. Roy

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2000
33EET. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Greg Spirakis, Naveed A. Sherwani, Craig Peterson: EDA challenges facing future microprocessor design. IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1498-1506 (2000)
1999
32 Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy: Characterizing Individual Gate Power Sensitivity in Low Power Design. VLSI Design 1999: 625-
31EEHuy Nguyen, Rabindra K. Roy, Abhijit Chatterjee: Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. J. Electronic Testing 14(3): 259-272 (1999)
1998
30 Sujit Dey, Anand Raghunathan, Rabindra K. Roy: Considering Testability during High-level Design (Embedded Tutorial). ASP-DAC 1998: 205-210
29EESrivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey: Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. VLSI Design 1998: 193-198
28 Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee: Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits. VLSI Design 1998: 199-204
27EESrivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey: Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electronic Testing 13(2): 201-212 (1998)
26EEHuy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy: Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. VLSI Signal Processing 18(1): 25-38 (1998)
1997
25EEHuy Nguyen, Abhijit Chatterjee, Rabindra K. Roy: Impact of Partial Reset on Fault Independent Testing and BIST. VLSI Design 1997: 537-539
24 Abhijit Chatterjee, Rabindra K. Roy: Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization. IEEE Trans. Computers 46(11): 1208-1218 (1997)
1996
23EESavita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy: Synchronous Test Generation Model for Asynchronous Circuits. VLSI Design 1996: 178-185
22EESrimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of initializable asynchronous circuits. IEEE Trans. VLSI Syst. 4(2): 254-263 (1996)
21EESavita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar: Initialization issues in asynchronous circuit synthesis. J. Electronic Testing 9(3): 237-250 (1996)
1995
20EEMiodrag Potkonjak, Sujit Dey, Rabindra K. Roy: Synthesis-for-testability using transformations. ASP-DAC 1995
19 Rabindra K. Roy: Advantages of High-Level Test Synthesis over Design for Test. ITC 1995: 293
18 Tam-Anh Chu, Rabindra K. Roy: Guest Editors' Introduction: More Practical Asynchronous Design. IEEE Design & Test of Computers 12(1): 13- (1995)
17EEMiodrag Potkonjak, Sujit Dey, Rabindra K. Roy: Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 531-546 (1995)
16EEMiodrag Potkonjak, Sujit Dey, Rabindra K. Roy: Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1141-1154 (1995)
1994
15 Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Signal Transition Graph Transformations for Initializability. EDAC-ETC-EUROASIC 1994: 670
14 Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Initialization Isuues in the Synthesis of Asynchronous Circuits. ICCD 1994: 447-452
13 Abhijit Chatterjee, Rabindra K. Roy: Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. VLSI Design 1994: 265-270
12 Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of Initializable Asynchronous Circuits. VLSI Design 1994: 383-388
11EETam-Anh Chu, Rabindra K. Roy: Guest Editor's Introduction: Practical Asynchronous Design. IEEE Design & Test of Computers 11(2): 6-7 (1994)
1993
10EEAbhijit Chatterjee, Rabindra K. Roy: An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. DAC 1993: 343-348
9EESujit Dey, Miodrag Potkonjak, Rabindra K. Roy: Exploiting hardware sharing in high-level synthesis for partial scan optimization. ICCAD 1993: 20-25
8 Abhijit Chatterjee, Rabindra K. Roy: Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. ICCD 1993: 606-609
7 Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu: Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. VLSI Design 1993: 154-159
6EEAbhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu: Greedy hardware optimization for linear digital circuits using number splitting and refactorization. IEEE Trans. VLSI Syst. 1(4): 423-431 (1993)
1992
5EERabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu: Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD 1992: 224-228
4EEThomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham: Test compaction for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 260-267 (1992)
3EEMiron Abramovici, David T. Miller, Rabindra K. Roy: Dynamic redundancy identification in automatic test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 404-407 (1992)
1991
2 Miron Abramovici, James J. Kulikowski, Rabindra K. Roy: The Best Flip-Flops to Scan. ITC 1991: 166-173
1988
1EEPatrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers: Fault Simulation in a Distributed Environment. DAC 1988: 686-691

Coauthor Index

1Jacob A. Abraham [1] [4] [5]
2Miron Abramovici [2] [3]
3Savita Banerjee [12] [14] [15] [21] [22] [23]
4Srimat T. Chakradhar [12] [14] [15] [21] [22] [23]
5Abhijit Chatterjee [5] [6] [7] [8] [10] [13] [24] [25] [26] [28] [31]
6Tam-Anh Chu [11] [18]
7Sujit Dey [9] [16] [17] [20] [27] [29] [30]
8Patrick A. Duba [1]
9Indradeep Ghosh [27] [29]
10T. Karn [33]
11Desmond Kirkpatrick [33]
12James J. Kulikowski [2]
13David T. Miller [3]
14Unni Narayanan [32]
15Huy Nguyen [25] [28] [31]
16Huy T. Nguyen [26]
17Thomas M. Niermann [4]
18Janak H. Patel [4] [5]
19Craig Peterson [33]
20Miodrag Potkonjak [9] [16] [17] [20]
21Dhiraj K. Pradhan [12] [14] [15] [22]
22Anand Raghunathan [30]
23Srivaths Ravi [27] [29]
24Shishpal Rawat [33]
25William A. Rogers [1]
26Naveed A. Sherwani [33]
27Greg Spirakis [33]
28Georgios I. Stamoulis [32]
29Manuel A. d'Abreu [5] [6] [7]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)