| 2009 |
|---|
| 13 | EE | Wan-Yu Lee,
Iris Hui-Ru Jiang:
VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.
ACM Great Lakes Symposium on VLSI 2009: 39-44 |
| 2008 |
|---|
| 12 | EE | Iris Hui-Ru Jiang,
Ming-Hua Wu:
Power-state-aware buffered tree construction.
ICCD 2008: 21-26 |
| 11 | EE | Iris Hui-Ru Jiang,
Yen-Ting Yu:
Configurable rectilinear Steiner tree construction for SoC and nano technologies.
ICCD 2008: 34-39 |
| 10 | EE | Iris Hui-Ru Jiang,
Shung-Wei Lin,
Yen-Ting Yu:
Unification of obstacle-avoiding rectilinear Steiner tree construction.
SoCC 2008: 127-130 |
| 2006 |
|---|
| 9 | EE | Iris Hui-Ru Jiang,
Song-Ra Pan,
Yao-Wen Chang,
Jing-Yang Jou:
Reliable crosstalk-driven interconnect optimization.
ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006) |
| 2004 |
|---|
| 8 | EE | Iris Hui-Ru Jiang,
Yao-Wen Chang,
Jing-Yang Jou,
Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004) |
| 2002 |
|---|
| 7 | EE | Nicholas Chia-Yuan Chang,
Yao-Wen Chang,
Iris Hui-Ru Jiang:
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.
ISQED 2002: 523-528 |
| 2000 |
|---|
| 6 | EE | Iris Hui-Ru Jiang,
Song-Ra Pan,
Yao-Wen Chang,
Jing-Yang Jou:
Optimal reliable crosstalk-driven interconnect optimization.
ISPD 2000: 128-133 |
| 5 | EE | Iris Hui-Ru Jiang,
Yao-Wen Chang,
Jing-Yang Jou:
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 999-1010 (2000) |
| 1999 |
|---|
| 4 | EE | Jiann-Horng Lin,
Jing-Yang Jou,
Iris Hui-Ru Jiang:
Hierarchical Floorplan Design on the Internet.
ASP-DAC 1999: 189-192 |
| 3 | EE | Iris Hui-Ru Jiang,
Jing-Yang Jou,
Yao-Wen Chang:
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.
DAC 1999: 90-95 |
| 2 | EE | Mango Chia-Tso Chao,
Guang-Ming Wu,
Iris Hui-Ru Jiang,
Yao-Wen Chang:
A clustering- and probability-based approach for time-multiplexed FPGA partitioning.
ICCAD 1999: 364-369 |
| 1 | EE | Jie-Hong Roland Jiang,
Iris Hui-Ru Jiang:
Optimum loading dispersion for high-speed tree-type decision circuitry.
ICCAD 1999: 520-525 |
