2003 |
23 | EE | Pak K. Chan,
Martine D. F. Schlag:
Parallel placement for field-programmable gate arrays.
FPGA 2003: 43-50 |
2000 |
22 | EE | Pak K. Chan,
Martine D. F. Schlag:
New parallelization and convergence results for NC: a negotiation-based FPGA router.
FPGA 2000: 165-174 |
21 | EE | Pak K. Chan,
Martine D. F. Schlag,
Carl Ebeling,
Larry McMurchie:
Distributed-memory parallel routing for field-programmable gatearrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 850-862 (2000) |
1999 |
20 | EE | Pak K. Chan,
Mark J. Boyd,
S. Goren,
K. Klenk,
V. Kodavati,
R. Kundu,
M. Margolese,
J. Sun,
K. Suzuki,
E. Thorne,
X. Wang,
J. Xu,
M. Zhu:
Reducing Compilation Time of Zhong's FPGA-Based SAT Solver.
FCCM 1999: 308-309 |
19 | EE | Jason Y. Zien,
Martine D. F. Schlag,
Pak K. Chan:
Multilevel spectral hypergraph partitioning with arbitrary vertex sizes.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1389-1399 (1999) |
1997 |
18 | EE | Pak K. Chan,
Martine D. F. Schlag:
Acceleration of an FPGA router.
FCCM 1997: 175-181 |
17 | EE | Jason Y. Zien,
Pak K. Chan,
Martine D. F. Schlag:
Hybrid spectral/iterative partitioning.
ICCAD 1997: 436-440 |
1996 |
16 | EE | Jason Y. Zien,
Martine D. F. Schlag,
Pak K. Chan:
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes.
ICCAD 1996: 201-204 |
15 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
Spectral-based multiway FPGA partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 554-560 (1996) |
1995 |
14 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
Spectral-Based Multi-Way FPGA Partitioning.
FPGA 1995: 133-139 |
1994 |
13 | EE | Martine D. F. Schlag,
Jackson Kong,
Pak K. Chan:
Routability-driven technology mapping for lookup table-based FPGA's.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 13-26 (1994) |
12 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
Spectral K-way ratio-cut partitioning and clustering.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1088-1096 (1994) |
1993 |
11 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
On Routability Prediction for Field-Programmable Gate Arrays.
DAC 1993: 326-330 |
10 | EE | Pak K. Chan,
Martine D. F. Schlag,
Jason Y. Zien:
Spectral K-Way Ratio-Cut Partitioning and Clustering.
DAC 1993: 749-754 |
9 | EE | Martine D. F. Schlag,
Pak K. Chan,
Jackson Kong:
Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 713-722 (1993) |
1992 |
8 | | Martine D. F. Schlag,
Jackson Kong,
Pak K. Chan:
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs.
ICCD 1992: 86-90 |
7 | | Pak K. Chan,
Martine D. F. Schlag,
Clark D. Thomborson,
Vojin G. Oklobdzija:
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.
IEEE Trans. Computers 41(8): 920-930 (1992) |
1991 |
6 | EE | Pak K. Chan:
Comments on `Asymptotic waveform evaluation for timing analysis'.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 1078-1079 (1991) |
1990 |
5 | EE | Pak K. Chan:
Algorithms for Library-Specific Sizing of Combinational Logic.
DAC 1990: 353-356 |
4 | | Pak K. Chan,
Martine D. F. Schlag:
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip.
IEEE Trans. Computers 39(8): 983-992 (1990) |
3 | EE | Pak K. Chan,
Kevin Karplus:
Computing signal delay in general RC networks by tree/link partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 898-902 (1990) |
1989 |
2 | EE | Pak K. Chan,
Kevin Karplus:
Computing Signal Delay in General RC Networks by Tree/Link Partitioning.
DAC 1989: 485-490 |
1 | EE | Pak K. Chan,
Martine D. F. Schlag:
Bounds on signal delay in RC mesh networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 581-589 (1989) |