| 2002 |
| 12 | EE | Mukund Sivaraman,
Shail Aditya:
Cycle-time aware architecture synthesis of custom hardware accelerators.
CASES 2002: 35-42 |
| 11 | EE | Vinod Kathail,
Shail Aditya,
Robert Schreiber,
B. Ramakrishna Rau,
Darren C. Cronquist,
Mukund Sivaraman:
PICO: Automatically Designing Custom Computers.
IEEE Computer 35(9): 39-47 (2002) |
| 10 | EE | Robert Schreiber,
Shail Aditya,
Scott A. Mahlke,
Vinod Kathail,
B. Ramakrishna Rau,
Darren C. Cronquist,
Mukund Sivaraman:
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.
VLSI Signal Processing 31(2): 127-142 (2002) |
| 2001 |
| 9 | EE | Mukund Sivaraman,
Andrzej J. Strojwas:
Path delay fault diagnosis and coverage-a metric and an estimationtechnique.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 440-457 (2001) |
| 2000 |
| 8 | EE | Mukund Sivaraman,
Andrzej J. Strojwas:
Primitive path delay faults: identification and their use in timinganalysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1347-1362 (2000) |
| 1997 |
| 7 | EE | Mukund Sivaraman,
Andrzej J. Strojwas:
Timing analysis based on primitive path delay fault identification.
ICCAD 1997: 182-189 |
| 6 | EE | Mukund Sivaraman,
Andrzej J. Strojwas:
Primitive Path Delay Fault Identification.
VLSI Design 1997: 95-100 |
| 1996 |
| 5 | EE | Mukund Sivaraman,
Andrzej J. Strojwas:
Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults.
ICCAD 1996: 494-501 |
| 4 | EE | Mukund Sivaraman,
Andrzej J. Strojwas:
Diagnosis of parametric path delay faults.
VLSI Design 1996: 412-417 |
| 3 | EE | Mukund Sivaraman,
Andrzej J. Strojwas:
A diagnosability metric for parametric path delay faults.
VTS 1996: 316-323 |
| 1995 |
| 2 | | Mukund Sivaraman,
Andrzej J. Strojwas:
Test Vector Generation for Parametric Path Delay Faults.
ITC 1995: 132-138 |
| 1994 |
| 1 | | Mukund Sivaraman,
Andrzej J. Strojwas:
Towards Incorporating Device Parameter Variations in Timing Analysis.
EDAC-ETC-EUROASIC 1994: 338-342 |