| 2007 |
|---|
| 6 | | Chiou-Kou Tung,
Yu-Cherng Hung,
Shao-Hui Shieh,
Guo-Shing Huang:
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System.
DDECS 2007: 199-202 |
| 2006 |
|---|
| 5 | EE | Chiou-Kou Tung,
Shao-Hui Shieh,
Yu-Cherng Hung,
Ming-Chien Tsai:
High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability.
APCCAS 2006: 614-617 |
| 2004 |
|---|
| 4 | | Jin-Hua Hong,
Bin-Yan Tsai,
Liang-Te Lu,
Shao-Hui Shieh:
A novel radix-4 bit-level modular multiplier for fast RSA cryptosystem.
ISCAS (2) 2004: 837-840 |
| 2003 |
|---|
| 3 | EE | Shao-Hui Shieh,
Cheng-Wen Wu:
Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition.
J. Inf. Sci. Eng. 19(6): 1015-1039 (2003) |
| 2000 |
|---|
| 2 | EE | Bin-Hong Lin,
Shao-Hui Shieh,
Cheng-Wen Wu:
A fast signature computation algorithm for LFSR and MISR.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1031-1040 (2000) |
| 1996 |
|---|
| 1 | EE | Bin-Hong Lin,
Shao-Hui Shieh,
Cheng-Wen Wu:
A MISR Computation Algorithm for Fast Signature Simulation.
Asian Test Symposium 1996: 213-218 |
