| |
| 2000 | ||
|---|---|---|
| 2 | EE | Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan: VERILAT: verification using logic augmentation and transformations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1041-1051 (2000) |
| 1996 | ||
| 1 | EE | Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee: VERILAT: verification using logic augmentation and transformations. ICCAD 1996: 88-95 |
| 1 | Mitrajit Chatterjee | [1] [2] |
| 2 | Dhiraj K. Pradhan | [1] [2] |