2008 |
11 | EE | James L. Hafner,
Veera Deenadhayalan,
Wendy Belluomini,
Krishnakumar Rao:
Undetected disk errors in RAID arrays.
IBM Journal of Research and Development 52(4-5): 413-426 (2008) |
10 | EE | Mohammad Banikazemi,
Jim Hafner,
Wendy Belluomini,
K. K. Rao,
Dan E. Poff,
Bülent Abali:
Flipstone: managing storage with fail-in-place and deferred maintenance service models.
Operating Systems Review 42(1): 54-62 (2008) |
2006 |
9 | EE | Wendy Belluomini,
Damir Jamsek,
Andrew K. Martin,
Chandler McDowell,
Robert K. Montoye,
Hung C. Ngo,
Jun Sawada:
Limited switch dynamic logic circuits for high-speed low-power circuit design.
IBM Journal of Research and Development 50(2-3): 277-286 (2006) |
2004 |
8 | | Ramyanshu Datta,
Jacob A. Abraham,
Robert K. Montoye,
Wendy Belluomini,
Hung C. Ngo,
Chandler McDowell,
Jente B. Kuang,
Kevin J. Nowka:
A low latency and low power dynamic Carry Save Adder.
ISCAS (2) 2004: 477-480 |
2001 |
7 | EE | Chris J. Myers,
Wendy Belluomini,
Kip Kallpack,
Eric Peskin,
Hao Zheng:
Timed circuits: a new paradigm for high-speed design.
ASP-DAC 2001: 335-340 |
6 | EE | Wendy Belluomini,
Chris J. Myers,
H. Peter Hofstee:
Timed circuit verification using TEL structures.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 129-146 (2001) |
2000 |
5 | EE | Wendy Belluomini,
Chris J. Myers:
Timed state space exploration using POSETs.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 501-520 (2000) |
1999 |
4 | EE | Wendy Belluomini,
Chris J. Myers,
H. Peter Hofstee:
Verification of Delayed-Reset Domino Circuits Using ATACS.
ASYNC 1999: 3-12 |
3 | EE | Robert Thacker,
Wendy Belluomini,
Chris J. Myers:
Timed Circuit Synthesis Using Implicit Methods.
VLSI Design 1999: 181-188 |
1998 |
2 | | Wendy Belluomini,
Chris J. Myers:
Verification of Timed Systems Using POSETs.
CAV 1998: 403-415 |
1997 |
1 | EE | Wendy Belluomini,
Chris J. Myers:
Efficient Timing Analysis Algorithms for Timed State Space Exploration.
ASYNC 1997: 88-100 |