| 2005 |
|---|
| 10 | | Christian Haubelt,
Marek Jersak,
Kai Richter,
Karsten Strehl,
Dirk Ziegenbein,
Rolf Ernst,
Jürgen Teich,
Lothar Thiele:
SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme.
GI Jahrestagung (2) 2005: 693-697 |
| 2001 |
|---|
| 9 | EE | Karsten Strehl,
Lothar Thiele,
Matthias Gries,
Dirk Ziegenbein,
Rolf Ernst,
Jürgen Teich:
FunState-an internal design representation for codesign.
IEEE Trans. VLSI Syst. 9(4): 524-544 (2001) |
| 2000 |
|---|
| 8 | EE | Karsten Strehl,
Claudio Moraga,
Karl-Heinz Temme,
Radomir S. Stankovic:
Fuzzy Decision Diagrams for the Representation, Analysis and Optimization of Rule Bases.
ISMVL 2000: 127-132 |
| 7 | EE | Karsten Strehl,
Lothar Thiele:
Interval diagrams for efficient symbolic verification of processnetworks.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 939-956 (2000) |
| 6 | | Lothar Thiele,
Jürgen Teich,
Karsten Strehl:
Regular state machines.
Parallel Algorithms Appl. 15(3-4): 265-300 (2000) |
| 1999 |
|---|
| 5 | EE | Karsten Strehl,
Lothar Thiele,
Dirk Ziegenbein,
Rolf Ernst,
Jürgen Teich:
Scheduling hardware/software systems using symbolic techniques.
CODES 1999: 173-177 |
| 4 | EE | Karsten Strehl,
Lothar Thiele:
Interval Diagram Techniques for Symbolic Model Checking of Petri Nets.
DATE 1999: 756-757 |
| 3 | EE | Lothar Thiele,
Karsten Strehl,
Dirk Ziegenbein,
Rolf Ernst,
Jürgen Teich:
FunState - an internal design representation for codesign.
ICCAD 1999: 558-565 |
| 2 | EE | Karsten Strehl:
Interval Diagrams: Increasing Efficiency of Symbolic Real-Time Verification.
RTCSA 1999: 488- |
| 1998 |
|---|
| 1 | EE | Karsten Strehl,
Lothar Thiele:
Symbolic model checking of process networks using interval diagram techniques.
ICCAD 1998: 686-692 |
