| 2008 |
| 19 | EE | Svetlana N. Yanushkevich,
Oleg Boulanov,
Adrian Stoica,
Vlad P. Shmerko:
Support of Interviewing Techniques in Physical Access Control Systems.
IWCF 2008: 147-158 |
| 2006 |
| 18 | EE | Svetlana N. Yanushkevich,
Vlad P. Shmerko,
Oleg Boulanov:
Embedding and Assembling Techniques for Spatial Computing Structure Design using Decision Trees and Diagrams.
ISMVL 2006: 29 |
| 2004 |
| 17 | EE | Svetlana N. Yanushkevich,
Vlad P. Shmerko,
L. Guy,
D. C. Lu:
Three Dimensional Multiple Valued Circuits Design Based on Single-Electron Logic.
ISMVL 2004: 275-280 |
| 2003 |
| 16 | EE | Vlad P. Shmerko,
Svetlana N. Yanushkevich:
Three-Dimensional Feedforward Neural Networks and Their Realization by Nano-Devices.
Artif. Intell. Rev. 20(3-4): 473-494 (2003) |
| 2002 |
| 15 | EE | Svetlana N. Yanushkevich,
Piotr Dziurzanski,
Vlad P. Shmerko:
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 1: LAR Based Model.
ISMVL 2002: 202-208 |
| 14 | EE | Anna M. Tomaszewska,
Svetlana N. Yanushkevich,
Vlad P. Shmerko:
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model.
ISMVL 2002: 209-215 |
| 13 | | Svetlana N. Yanushkevich,
Vlad P. Shmerko,
V. D. Malyugin,
Piotr Dziurzanski:
Linearity of World-Level Circuit Models: New Understanding.
IWLS 2002: 67-72 |
| 2001 |
| 12 | | V. Cheushev,
Svetlana N. Yanushkevich,
Vlad P. Shmerko,
Claudio Moraga,
Joanna Kolodziejczyk:
Information Theory Method for Flexible Network Synthesis.
ISMVL 2001: 201-206 |
| 11 | | Anna M. Tomaszewska,
Piotr Dziurzanski,
Svetlana N. Yanushkevich,
Vlad P. Shmerko:
Two-Stage Exact Detection of Symmetrics.
ISMVL 2001: 213- |
| 10 | | Jon T. Butler,
Gerhard W. Dueck,
Svetlana N. Yanushkevich,
Vlad P. Shmerko:
On the number of generators for transeunt triangles.
Discrete Applied Mathematics 108(3): 309-316 (2001) |
| 2000 |
| 9 | EE | Tadeusz Luba,
Claudio Moraga,
Svetlana N. Yanushkevich,
Vlad P. Shmerko,
Joanna Kolodziejczyk:
Application of Design Style in Evolutionary Multi-Level Networks Synthesis.
EUROMICRO 2000: 1156-1163 |
| 8 | EE | Svetlana N. Yanushkevich,
Jon T. Butler,
Gerhard W. Dueck,
Vlad P. Shmerko:
Experiments on FPRM Expressions for Partially Symmetric Logic Functions.
ISMVL 2000: 141-146 |
| 7 | EE | Tadeusz Luba,
Claudio Moraga,
Svetlana N. Yanushkevich,
M. Opoka,
Vlad P. Shmerko:
Evolutionary Multi-Level Network Synthesis in Given Design Style.
ISMVL 2000: 253-258 |
| 6 | EE | Svetlana N. Yanushkevich,
Denis V. Popel,
Vlad P. Shmerko,
V. Cheushev,
Radomir S. Stankovic:
Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4).
ISMVL 2000: 265- |
| 5 | EE | Jon T. Butler,
Gerhard W. Dueck,
Vlad P. Shmerko,
Svetlana N. Yanushkevich:
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions".
IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1386-1388 (2000) |
| 1998 |
| 4 | EE | V. Cheushev,
Vlad P. Shmerko,
Dan A. Simovici,
Svetlana N. Yanushkevich:
Functional Entropy and Decision Trees.
ISMVL 1998: 257- |
| 1997 |
| 3 | EE | Vlad P. Shmerko,
Svetlana N. Yanushkevich,
Vitaly G. Levashenko:
Test Pattern Generation for Combinatorial Multi-Valued Networks Based on Generalized D-Algorithm.
ISMVL 1997: 139-144 |
| 1996 |
| 2 | EE | Vlad P. Shmerko,
Svetlana N. Yanushkevich,
Vitaly G. Levashenko,
I. Bondar:
Technique of Computing Logic Derivatives for MVL-Functions.
ISMVL 1996: 267-272 |
| 1 | | Vlad P. Shmerko,
Svetlana N. Yanushkevich,
K. Malecki:
A Class of Logic design Problems solved based on Parallel Computations of Butterfly Configurations.
PDPTA 1996: 1589-1592 |