José Luis Neves

2002
19	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Journal of Circuits, Systems, and Computers 11(3): 305- (2002)
2001
18	EE	Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402
17	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Exploiting the on-chip inductance in high-speed clock distribution networks. IEEE Trans. VLSI Syst. 9(6): 963-973 (2001)
16	EE	Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001)
2000
15	EE	José Luis Neves, Stephen T. Quay: Buffer Library Selection. ICCD 2000: 221-226
14	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore delay for RLC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 83-97 (2000)
1999
13	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore Delay for RLC Trees. DAC 1999: 715-720
12	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Great Lakes Symposium on VLSI 1999: 56-59
11	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Repeater insertion in tree structured inductive interconnect. ICCAD 1999: 420-424
10	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Signal waveform characterization in RLC trees. ISCAS (6) 1999: 190-193
9	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of merit to characterize the importance of on-chip inductance. IEEE Trans. VLSI Syst. 7(4): 442-449 (1999)
1998
8	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of Merit to Characterize the Importance of On-Chip Inductance. DAC 1998: 560-565
7	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. Great Lakes Symposium on VLSI 1998: 39-44
6	EE	Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Power dissipated by CMOS gates driving lossless transmission lines. ISLPED 1998: 139-142
1997
5	EE	José Luis Neves, Eby G. Friedman: Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. VLSI Signal Processing 16(2-3): 149-161 (1997)
1996
4	EE	José Luis Neves, Eby G. Friedman: Optimal Clock Skew Scheduling Tolerant to Process Variations. DAC 1996: 623-628
3	EE	José Luis Neves, Eby G. Friedman: Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. IEEE Trans. VLSI Syst. 4(2): 286-291 (1996)
1995
2		José Luis Neves, Eby G. Friedman: Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. ISCAS 1995: 1576-1579
1994
1		José Luis Neves, Eby G. Friedman: Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. ISCAS 1994: 175-178

Coauthor Index

1	Charles J. Alpert	[16] [18]
2	Eby G. Friedman	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [17] [19]
3	Gopal Gandham	[16] [18]
4	Jiang Hu	[16] [18]
5	Yehea I. Ismail	[6] [7] [8] [9] [10] [11] [12] [13] [14] [17] [19]
6	Stephen T. Quay	[15] [16] [18]
7	Sachin S. Sapatnekar	[16] [18]

Colors in the list of coauthors