| 2000 |
|---|
| 6 | EE | Guenter Stenz,
Bernhard M. Riess,
Bernhard Rohfleisch,
Frank M. Johannes:
Performance optimization by interacting netlist transformations andplacement.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 350-358 (2000) |
| 1998 |
|---|
| 5 | EE | Soren Hein,
Vijay Nagasamy,
Bernhard Rohfleisch,
Christoforos E. Kozyrakis,
Nikil D. Dutt,
Francky Catthoor:
Embedded memories in system design - from technology to systems architecture.
ICCAD 1998: 1 |
| 1997 |
|---|
| 4 | EE | Guenter Stenz,
Bernhard M. Riess,
Bernhard Rohfleisch,
Frank M. Johannes:
Timing driven placement in interaction with netlist transformations.
ISPD 1997: 36-41 |
| 1996 |
|---|
| 3 | EE | Bernhard Rohfleisch,
Alfred Kölbl,
Bernd Wurth:
Reducing Power Dissipation after Technology Mapping by Structural Transformations.
DAC 1996: 789-794 |
| 1995 |
|---|
| 2 | EE | Bernhard Rohfleisch,
Bernd Wurth,
Kurt Antreich:
Logic Clause Analysis for Delay Optimization.
DAC 1995: 668-672 |
| 1994 |
|---|
| 1 | | Bernhard Rohfleisch,
Franc Brglez:
Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping.
EDAC-ETC-EUROASIC 1994: 87-93 |
