1997 |
14 | EE | Zhiyu Tian,
Ting-Ting Y. Lin,
Shiyuan Yang,
Shibai Tong:
The Faulty Behavior of Feedforward Neural Networks with Hard-limiting Activation Fuction.
Neural Computation 9(5): 1109-1126 (1997) |
1996 |
13 | EE | Huoy-Yu Liou,
Ting-Ting Y. Lin,
Chung-Kuan Cheng:
Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming.
DAC 1996: 274-279 |
12 | EE | John Lillis,
Chung-Kuan Cheng,
Ting-Ting Y. Lin,
Chin-Yen Ho:
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.
DAC 1996: 395-400 |
11 | EE | John Lillis,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
Simultaneous Routing and Buffer Insertion for High Performance Interconnect.
Great Lakes Symposium on VLSI 1996: 148-153 |
1995 |
10 | EE | Chia-Chun Tsai,
De-Yu Kao,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
Performance driven multiple-source bus synthesis using buffer insertion.
ASP-DAC 1995 |
9 | EE | John Lillis,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model.
ICCAD 1995: 138-143 |
8 | EE | Jae W. Chung,
De-Yu Kao,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
Optimization of power dissipation and skew sensitivity in clock buffer synthesis.
ISLPD 1995: 179-184 |
7 | EE | Ching-Wei Yeh,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
Optimization by iterative improvement: an experimental evaluation on two-way partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 145-153 (1995) |
6 | EE | Ching-Wei Yeh,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
Circuit clustering using a stochastic flow injection method.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 154-162 (1995) |
1994 |
5 | EE | Ching-Wei Yeh,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
A general purpose, multiple-way partitioning algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1480-1488 (1994) |
1993 |
4 | | Amiya Bhattacharya,
Ramesh R. Rao,
Ting-Ting Y. Lin:
Delay Analysis in Synchronous Circuit-Switched Delta Networks.
IPPS 1993: 666-670 |
3 | EE | Ting-Ting Y. Lin,
Huoy-Yu Liou:
A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy.
IEEE Design & Test of Computers 10(4): 38-51 (1993) |
1992 |
2 | EE | Ching-Wei Yeh,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
A probabilistic multicommodity-flow solution to circuit clustering problems.
ICCAD 1992: 428-431 |
1991 |
1 | EE | Ching-Wei Yeh,
Chung-Kuan Cheng,
Ting-Ting Y. Lin:
A General Purpose Multiple Way Partitioning Algorithm.
DAC 1991: 421-426 |