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Ting-Ting Y. Lin

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1997
14EEZhiyu Tian, Ting-Ting Y. Lin, Shiyuan Yang, Shibai Tong: The Faulty Behavior of Feedforward Neural Networks with Hard-limiting Activation Fuction. Neural Computation 9(5): 1109-1126 (1997)
1996
13EEHuoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng: Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. DAC 1996: 274-279
12EEJohn Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho: New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. DAC 1996: 395-400
11EEJohn Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin: Simultaneous Routing and Buffer Insertion for High Performance Interconnect. Great Lakes Symposium on VLSI 1996: 148-153
1995
10EEChia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin: Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC 1995
9EEJohn Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimal wire sizing and buffer insertion for low power and a generalized delay model. ICCAD 1995: 138-143
8EEJae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimization of power dissipation and skew sensitivity in clock buffer synthesis. ISLPD 1995: 179-184
7EEChing-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: Optimization by iterative improvement: an experimental evaluation on two-way partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 145-153 (1995)
6EEChing-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: Circuit clustering using a stochastic flow injection method. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 154-162 (1995)
1994
5EEChing-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A general purpose, multiple-way partitioning algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1480-1488 (1994)
1993
4 Amiya Bhattacharya, Ramesh R. Rao, Ting-Ting Y. Lin: Delay Analysis in Synchronous Circuit-Switched Delta Networks. IPPS 1993: 666-670
3EETing-Ting Y. Lin, Huoy-Yu Liou: A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy. IEEE Design & Test of Computers 10(4): 38-51 (1993)
1992
2EEChing-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A probabilistic multicommodity-flow solution to circuit clustering problems. ICCAD 1992: 428-431
1991
1EEChing-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin: A General Purpose Multiple Way Partitioning Algorithm. DAC 1991: 421-426

Coauthor Index

1Amiya Bhattacharya [4]
2Chung-Kuan Cheng [1] [2] [5] [6] [7] [8] [9] [10] [11] [12] [13]
3Jae W. Chung [8]
4Chin-Yen Ho [12]
5De-Yu Kao [8] [10]
6John Lillis [9] [11] [12]
7Huoy-Yu Liou [3] [13]
8Ramesh R. Rao [4]
9Zhiyu Tian [14]
10Shibai Tong [14]
11Chia-Chun Tsai [10]
12Shiyuan Yang [14]
13Chingwei Yeh (Ching-Wei Yeh) [1] [2] [5] [6] [7]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)