| |
| 2004 | ||
|---|---|---|
| 2 | EE | Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda: Design methodology and tools for NEC electronics' structured ASIC ISSP. ISPD 2004: 90-96 |
| 1996 | ||
| 1 | EE | Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emura, Naotaka Maeda: Post-Layout Optimization for Deep Submicron Design. DAC 1996: 740-745 |
| 1 | Hideyuki Emura | [1] |
| 2 | Masamichi Kawarabayashi | [1] |
| 3 | Tsutomu Kimoto | [2] |
| 4 | Takumi Okamoto | [2] |
| 5 | Koichi Sato | [1] |