| 2000 |
|---|
| 68 | EE | Gayles Gayles,
Thomas P. Kelliher,
Robert Michael Owens,
Mary Jane Irwin:
The design of the MGAP-2: a micro-grained massively parallel array.
IEEE Trans. VLSI Syst. 8(6): 709-716 (2000) |
| 1999 |
|---|
| 67 | EE | Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
A Fast and Simple Steiner Routing Heuristic.
Discrete Applied Mathematics 90(1-3): 51-67 (1999) |
| 66 | EE | Benjamin Bishop,
Thomas P. Kelliher,
Robert Michael Owens,
Mary Jane Irwin:
Aggressive Dynamic Execution of Decoded Traces.
VLSI Signal Processing 22(1): 65-75 (1999) |
| 1998 |
|---|
| 65 | EE | Rita Yu Chen,
Robert Michael Owens,
Mary Jane Irwin,
Raminder Singh Bajwa:
Validation of an Architectural Level Power Analysis Technique.
DAC 1998: 242-245 |
| 64 | EE | Benjamin Bishop,
Robert Michael Owens,
Mary Jane Irwin:
Aggressive Dynamic Execution of Multimedia Kernel Traces.
IPPS/SPDP 1998: 640-646 |
| 63 | EE | Kevin P. Acken,
Mary Jane Irwin,
Robert Michael Owens:
A Parallel ASIC Architecture for Efficient Fractal Image Coding.
VLSI Signal Processing 19(2): 97-113 (1998) |
| 62 | EE | Robert Michael Owens,
Mohan Vishwanath:
A Very Efficient Storage Structure for DWT and IDWT Filters.
VLSI Signal Processing 19(3): 215-225 (1998) |
| 1997 |
|---|
| 61 | EE | Kevin P. Acken,
Eric Gayles,
Thomas P. Kelliher,
Robert Michael Owens,
Mary Jane Irwin:
The MGAP Family of Processor Arrays.
Great Lakes Symposium on VLSI 1997: 105- |
| 60 | EE | Eric Gayles,
Kevin P. Acken,
Robert Michael Owens,
Mary Jane Irwin:
A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines.
Great Lakes Symposium on VLSI 1997: 182- |
| 59 | EE | Patrick Hicks,
Matthew Walnock,
Robert Michael Owens:
Analysis of power consumption in memory hierarchies.
ISLPED 1997: 239-242 |
| 58 | EE | Huzefa Mehta,
Robert Michael Owens,
Mary Jane Irwin,
Rita Yu Chen,
Debashree Ghosh:
Techniques for low energy software.
ISLPED 1997: 72-75 |
| 57 | EE | Huzefa Mehta,
Robert Michael Owens,
Mary Jane Irwin:
A Simulation Methodology for Software Energy Evaluation.
VLSI Design 1997: 509-510 |
| 56 | EE | Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
A fast algorithm for minimizing the Elmore delay to identified critical sinks.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 753-759 (1997) |
| 55 | EE | Heung-Nam Kim,
Mary Jane Irwin,
Robert Michael Owens:
Motion Analysis on the Micro Grained Array Processor.
Real-Time Imaging 3(2): 101-110 (1997) |
| 1996 |
|---|
| 54 | EE | Mohan Vishwanath,
Robert Michael Owens:
A Common Architecture For The DWT and IDWT.
ASAP 1996: 193-198 |
| 53 | EE | Kevin P. Acken,
Heung-Nam Kim,
Mary Jane Irwin,
Robert Michael Owens:
An Architectural Design For Parallel Fractal Compression.
ASAP 1996: 3-11 |
| 52 | EE | Kevin P. Acken,
Mary Jane Irwin,
Robert Michael Owens,
Amulya K. Garga:
Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline.
ASAP 1996: 65-71 |
| 51 | EE | Huzefa Mehta,
Robert Michael Owens,
Mary Jane Irwin:
Energy Characterization based on Clustering.
DAC 1996: 702-707 |
| 50 | EE | Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
Recent Developments in Performance Driven Steiner Routing: An Overview.
Great Lakes Symposium on VLSI 1996: 137-142 |
| 49 | EE | Huzefa Mehta,
Robert Michael Owens,
Mary Jane Irwin:
Some Issues in Gray Code Addressing.
Great Lakes Symposium on VLSI 1996: 178-181 |
| 48 | EE | Kevin P. Acken,
Mary Jane Irwin,
Robert Michael Owens:
Power comparisons for barrel shifters.
ISLPED 1996: 209-212 |
| 47 | EE | Chetana Nagendra,
Robert Michael Owens,
Mary Jane Irwin:
Design tradeoffs in high speed multipliers and FIR filters.
VLSI Design 1996: 29-32 |
| 46 | EE | Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
Transistor sizing for low power CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 665-671 (1996) |
| 45 | EE | Manjit Borah,
Chetana Nagendra,
Mohan Vishwanath,
Robert Michael Owens,
Mary Jane Irwin:
An optimal time multiplication free algorithm for edge detection on a mesh.
VLSI Signal Processing 13(1): 67-75 (1996) |
| 44 | EE | Chaitali Chakrabarti,
Mohan Vishwanath,
Robert Michael Owens:
Architectures for wavelet transforms: A survey.
VLSI Signal Processing 14(2): 171-192 (1996) |
| 1995 |
|---|
| 43 | EE | Raminder Singh Bajwa,
Robert Michael Owens,
Mary Jane Irwin:
The MGAP's programming environment and the *C++ language.
ASAP 1995: 121-124 |
| 42 | EE | Heung-Nam Kim,
Mary Jane Irwin,
Robert Michael Owens:
Motion Estimation Algorithms on Fine Grain Array Processor.
ASAP 1995: 204-213 |
| 41 | EE | Huzefa Mehta,
Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
Accurate Estimation of Combinational Circuit Activity.
DAC 1995: 618-622 |
| 40 | EE | Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
Fast algorithm for performance-oriented Steiner routing.
Great Lakes Symposium on VLSI 1995: 198-203 |
| 39 | EE | Robert Michael Owens,
Raminder Singh Bajwa,
Mary Jane Irwin:
Reducing the number of counters needed for integer multiplication.
IEEE Symposium on Computer Arithmetic 1995: 38-41 |
| 38 | EE | Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
High-throughput and low-power DSP using clocked-CMOS circuitry.
ISLPD 1995: 139-144 |
| 37 | EE | Chetana Nagendra,
Robert Michael Owens,
Mary Jane Irwin:
Unifying carry-sum and signed-digital number representations for low power.
ISLPD 1995: 15-20 |
| 36 | EE | Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint.
ISLPD 1995: 167-172 |
| 35 | EE | Manjit Borah,
Mary Jane Irwin,
Robert Michael Owens:
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.
VLSI Design 1995: 294-298 |
| 34 | EE | Chetana Nagendra,
Robert Michael Owens,
Mary Jane Irwin:
Digit pipelined arithmetic on fine-grain array processors.
VLSI Signal Processing 9(3): 193-209 (1995) |
| 1994 |
|---|
| 33 | | Manjit Borah,
Chetana Nagendra,
Robert Michael Owens,
Mary Jane Irwin:
The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS.
HICSS (1) 1994: 96-104 |
| 32 | | Heung-Nam Kim,
Mary Jane Irwin,
Robert Michael Owens,
Chen-Mi Wu:
Dynamic Space Warping Algorithms on Fine-Graln Array Processors.
IPPS 1994: 921-925 |
| 31 | | Mary Sue Haydt,
Robert Michael Owens,
Samiha Mourad:
Modeling the Effect of Ground Bounce on Noise Margin.
ITC 1994: 279-285 |
| 30 | | Raminder Singh Bajwa,
Robert Michael Owens,
Mary Jane Irwin:
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.
IEEE Trans. Computers 43(10): 1121-1128 (1994) |
| 29 | | Gueesang Lee,
Mary Jane Irwin,
Robert Michael Owens:
Polynomial Time Testability of Circuits Generated by Input Decomposition.
IEEE Trans. Computers 43(2): 201-210 (1994) |
| 28 | EE | Chetana Nagendra,
Robert Michael Owens,
Mary Jane Irwin:
Power-delay characteristics of CMOS adders.
IEEE Trans. VLSI Syst. 2(3): 377-381 (1994) |
| 27 | EE | TingTing Hwang,
Robert Michael Owens,
Mary Jane Irwin,
Kuo-Hua Wang:
Logic synthesis for field-programmable gate arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1280-1287 (1994) |
| 26 | EE | Manjit Borah,
Robert Michael Owens,
Mary Jane Irwin:
An edge-based heuristic for Steiner routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1563-1568 (1994) |
| 1993 |
|---|
| 25 | | Raminder Singh Bajwa,
Robert Michael Owens,
Mary Jane Irwin:
Image Processing with the MGAP: A Cost Effective Solution.
IPPS 1993: 439-443 |
| 24 | | Raminder Singh Bajwa,
Robert Michael Owens,
Mary Jane Irwin:
A Massively Parallel, Micro-Grained VLSI Architecture.
VLSI Design 1993: 250-255 |
| 23 | EE | Robert Michael Owens,
Thomas P. Kelliher,
Mary Jane Irwin,
Mohan Vishwanath,
Raminder Singh Bajwa,
W.-L. Yang:
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
IEEE Trans. VLSI Syst. 1(4): 491-502 (1993) |
| 1992 |
|---|
| 22 | EE | Soohong Kim,
Robert Michael Owens,
Mary Jane Irwin:
Experiments with a Performance Driven Module Generator.
DAC 1992: 687-690 |
| 21 | | Thomas P. Kelliher,
Robert Michael Owens,
Mary Jane Irwin,
TingTing Hwang:
ELM-A Fast Addition Algorithm Discovered by a Program.
IEEE Trans. Computers 41(9): 1181-1184 (1992) |
| 20 | EE | TingTing Hwang,
Robert Michael Owens,
Mary Jane Irwin:
Efficiently computing communication complexity for multilevel logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 545-554 (1992) |
| 1991 |
|---|
| 19 | | Mary Jane Irwin,
Robert Michael Owens:
A Two-Dimensional, Distributed Logic Architecture.
IEEE Trans. Computers 40(10): 1094-1101 (1991) |
| 18 | | Poras T. Balsara,
Robert Michael Owens,
Mary Jane Irwin:
Digit Serial Multipliers.
J. Parallel Distrib. Comput. 11(2): 156-162 (1991) |
| 1990 |
|---|
| 17 | | Robert Michael Owens,
Mary Jane Irwin:
Being Stingy with Multipliers.
IEEE Trans. Computers 39(6): 809-818 (1990) |
| 16 | EE | TingTing Hwang,
Robert Michael Owens,
Mary Jane Irwin:
Exploiting communication complexity for multilevel logic synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1017-1027 (1990) |
| 15 | EE | Mary Jane Irwin,
Robert Michael Owens:
A case for digit serial VLSI signal processors.
VLSI Signal Processing 1(4): 321-334 (1990) |
| 1989 |
|---|
| 14 | EE | TingTing Hwang,
Robert Michael Owens,
Mary Jane Irwin:
Multi-Level Logic Synthesis Using Communication Complexity.
DAC 1989: 215-220 |
| 13 | EE | Mary Jane Irwin,
Robert Michael Owens:
A Comparison of Four Two-dimensional Gate Matrix Layout Tools.
DAC 1989: 698-701 |
| 1988 |
|---|
| 12 | EE | Pao-Po Hou,
Robert Michael Owens,
Mary Jane Irwin:
DECOMPOSER: A Synthesizer for Systolic Systems.
DAC 1988: 650-653 |
| 1987 |
|---|
| 11 | EE | J. A. Beekman,
Robert Michael Owens,
Mary Jane Irwin:
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation.
DAC 1987: 357-362 |
| 10 | EE | Robert Michael Owens,
Mary Jane Irwin:
An Overview of the Penn State Design System.
DAC 1987: 516-522 |
| 9 | | Mary Jane Irwin,
Robert Michael Owens:
Digit-Pipelined Arithmetic as Illustrated By the Paste-Up System: A Tutorial.
IEEE Computer 20(4): 61-73 (1987) |
| 8 | | Robert Michael Owens,
Mary Jane Irwin:
The Arithmetic Cube.
IEEE Trans. Computers 36(11): 1342-1348 (1987) |
| 1986 |
|---|
| 7 | | Robert Michael Owens,
Joseph JáJá:
Optimal Algorithms for Mesh-Connected Parallel Processors with Serial Memories.
ICPP 1986: 812-818 |
| 6 | EE | Robert Michael Owens,
Mary Jane Irwin:
A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(3): 420-428 (1986) |
| 1985 |
|---|
| 5 | | Robert Michael Owens,
Joseph JáJá:
Parallel Sorting with Serial Momories.
IEEE Trans. Computers 34(4): 379-383 (1985) |
| 1984 |
|---|
| 4 | | Joseph JáJá,
Robert Michael Owens:
VLSI Sorting with Reduced Hardware.
IEEE Trans. Computers 33(7): 668-671 (1984) |
| 1983 |
|---|
| 3 | | Mary Jane Irwin,
Robert Michael Owens:
Fully Digit On-Line Networks.
IEEE Trans. Computers 32(4): 402-406 (1983) |
| 2 | | Robert Michael Owens:
Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic.
IEEE Trans. Computers 32(4): 406-411 (1983) |
| 1979 |
|---|
| 1 | | Robert Michael Owens,
Mary Jane Irwin:
On-Line Algorithms for the Design of Pipeline Architectures.
ISCA 1979: 12-19 |
