| 1996 |
|---|
| 6 | EE | Manish Pandey,
Richard Raimi,
Derek L. Beatty,
Randal E. Bryant:
Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation.
DAC 1996: 649-654 |
| 1995 |
|---|
| 5 | EE | Manish Pandey,
Alok Jain,
Randal E. Bryant,
Derek L. Beatty,
Gary York,
Samir Jain:
Extraction of finite state machines from transistor netlists by symbolic simulation.
ICCD 1995: 596-601 |
| 1994 |
|---|
| 4 | EE | Derek L. Beatty,
Randal E. Bryant:
Formally Verifying a Microprocessor Using a Simulation Methodology.
DAC 1994: 596-602 |
| 1991 |
|---|
| 3 | EE | Randal E. Bryant,
Derek L. Beatty,
Carl-Johan H. Seger:
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation.
DAC 1991: 397-402 |
| 1988 |
|---|
| 2 | EE | Derek L. Beatty,
Randal E. Bryant:
Fast Incremental Circuit Analysis Using Extracted Hierarchy.
DAC 1988: 495-500 |
| 1987 |
|---|
| 1 | EE | Randal E. Bryant,
Derek L. Beatty,
Karl S. Brace,
K. Cho,
Thomas J. Sheffler:
COSMOS: A Compiled Simulator for MOS Circuits.
DAC 1987: 9-16 |
