2004 |
27 | EE | G. Venkatesh:
Reasoning About Game Equilibria Using Temporal Logic.
FSTTCS 2004: 506-517 |
1998 |
26 | EE | Mahesh Mehendale,
Somdipta Basu Roy,
Sunil D. Sherlekar,
G. Venkatesh:
Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters.
VLSI Design 1998: 110-115 |
25 | EE | Mahesh Mehendale,
Sunil D. Sherlekar,
G. Venkatesh:
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.
VLSI Design 1998: 12-17 |
24 | EE | Mahesh Mehendale,
Sunil D. Sherlekar,
G. Venkatesh:
Extensions to Programmable DSP architectures for Reduced Power Dissipation.
VLSI Design 1998: 37- |
23 | EE | Mahesh Mehendale,
Sunil D. Sherlekar,
G. Venkatesh:
Low-power realization of FIR filters on programmable DSPs.
IEEE Trans. VLSI Syst. 6(4): 546-553 (1998) |
22 | | Manoranjan Satpathy,
Amitabha Sanyal,
G. Venkatesh:
Improved Register Usage for Functional Programs through Multiple Function Versions.
Journal of Functional and Logic Programming 1998(7): (1998) |
1997 |
21 | EE | Mahesh Mehendale,
Sunil D. Sherlekar,
G. Venkatesh:
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters.
VLSI Design 1997: 124-129 |
1996 |
20 | EE | Mahesh Mehendale,
G. Venkatesh,
Sunil D. Sherlekar:
Optimized Code Generation of Multiplication-free Linear Transforms.
DAC 1996: 41-46 |
19 | | Milind Gandhe,
G. Venkatesh,
Amitabha Sanyal:
Correcting Errors in the Curry System.
FSTTCS 1996: 347-358 |
18 | EE | Mahesh Mehendale,
Sunil D. Sherlekar,
G. Venkatesh:
Low power realization of FIR filters using multirate architectures.
VLSI Design 1996: 370-375 |
17 | EE | Rubin A. Parekhji,
G. Venkatesh,
Sunil D. Sherlekar:
Monitoring machine based synthesis technique for concurrent error detection in finite state machines.
J. Electronic Testing 8(2): 179-201 (1996) |
16 | | Mohsin Ahmed,
G. Venkatesh:
Dense Time Logic Programming.
J. Symb. Comput. 22(5/6): 585-613 (1996) |
1995 |
15 | | Milind Gandhe,
G. Venkatesh,
Amitabha Sanyal:
Labeled Lambda-Calculus and a Generalized Notion of Strictness (An Extended Abstract).
ASIAN 1995: 103-110 |
14 | | Manoranjan Satpathy,
Amitabha Sanyal,
G. Venkatesh:
An Automaton-Driven Frame Disposal Algorithm and its Proof of Correctness.
ASIAN 1995: 88-102 |
13 | EE | Mahesh Mehendale,
Sunil D. Sherlekar,
G. Venkatesh:
Techniques for low power realization for FIR filters.
ASP-DAC 1995 |
12 | EE | Mahesh Mehendale,
Sunil D. Sherlekar,
G. Venkatesh:
Synthesis of multiplier-less FIR filters with minimum number of additions.
ICCAD 1995: 668-671 |
11 | EE | B. Ravi Kishore,
Rubin A. Parekhji,
Sandeep Pagey,
Sunil D. Sherlekar,
G. Venkatesh:
A new methodology for the design of low-cost fail safe circuits and networks.
VLSI Design 1995: 355-358 |
10 | EE | Rubin A. Parekhji,
G. Venkatesh,
Sunil D. Sherlekar:
Concurrent Error Detection Using Monitoring Machines.
IEEE Design & Test of Computers 12(3): 24-32 (1995) |
1993 |
9 | | Mohsin Ahmed,
G. Venkatesh:
A Propositional Dense Time Logic (Based on Nested Sequences).
TAPSOFT 1993: 584-598 |
8 | | Rubin A. Parekhji,
G. Venkatesh,
Sunil D. Sherlekar:
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits.
VLSI Design 1993: 15-20 |
1992 |
7 | EE | Ajay Khoche,
Sunil D. Sherlekar,
G. Venkatesh,
Raja Venkateswaran:
A Behavioral Fault Simulator for Ideal.
IEEE Design & Test of Computers 9(4): 14-21 (1992) |
1991 |
6 | | Rubin A. Parekhji,
G. Venkatesh,
Sunil D. Sherlekar:
A Methodology for Designing Optimal Self-Checking Sequential Circuits.
ITC 1991: 283-291 |
5 | EE | Sandeep Pagey,
Sunil D. Sherlekar,
G. Venkatesh:
A methodology for the design of SFS/SCD circuits for a class of unordered codes.
J. Electronic Testing 2(3): 261-277 (1991) |
1989 |
4 | | Milind Gandhe,
G. Venkatesh:
Improving Prolog Performance by Inductive Proof Generalizations.
KBCS 1989: 243-253 |
1986 |
3 | EE | S. Bapat,
G. Venkatesh:
Reasoning about digital systems using temporal logic.
DAC 1986: 215-219 |
1985 |
2 | | G. Venkatesh:
A Decision Method for Temporal Logic Based on Resolution.
FSTTCS 1985: 272-289 |
1982 |
1 | | Donald F. Towsley,
G. Venkatesh:
Window Random Access Protocols for Local Computer Networks.
IEEE Trans. Computers 31(8): 715-722 (1982) |