Yusuke Matsunaga

2009
30	EE	Taiga Takata, Yusuke Matsunaga: An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI 2009: 351-356
2008
29	EE	Taiga Takata, Yusuke Matsunaga: Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. ASP-DAC 2008: 144-147
28	EE	Tsuyoshi Sadakata, Yusuke Matsunaga: An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. ASP-DAC 2008: 32-35
27	EE	Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga: Synthesis of parallel prefix adders considering switching activities. ICCD 2008: 404-409
26	EE	Tsuyoshi Sadakata, Yusuke Matsunaga: A Behavioral Synthesis Method with Special Functional Units. IEICE Transactions 91-A(4): 1084-1091 (2008)
2007
25	EE	Taeko Matsunaga, Yusuke Matsunaga: Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ACM Great Lakes Symposium on VLSI 2007: 435-440
24	EE	Yusuke Matsunaga: Special Section on VLSI Design and CAD Algorithms. IEICE Transactions 90-A(12): 2649-2650 (2007)
23	EE	Taeko Matsunaga, Yusuke Matsunaga: Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. IEICE Transactions 90-A(12): 2770-2777 (2007)
22	EE	Yusuke Matsunaga: Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa. IEICE Transactions 90-A(4): 705-706 (2007)
21	EE	Tsuyoshi Sadakata, Yusuke Matsunaga: A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units. IEICE Transactions 90-A(4): 792-799 (2007)
20	EE	Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki Murakami: Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Transactions 90-C(5): 1012-1020 (2007)
2006
19	EE	Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura: A character size optimization technique for throughput enhancement of character projection lithography. ISCAS 2006
18	EE	Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki Murakami, Katsuya Okumura: Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Transactions 89-C(3): 377-383 (2006)
2004
17	EE	Hiroyuki Higuchi, Yusuke Matsunaga: Enhancing the performance of multi-cycle path analysis in an industrial setting. ASP-DAC 2004: 192-197
16	EE	Makoto Sugihara, Kazuaki Murakami, Yusuke Matsunaga: Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI 2004: 179-186
2002
15	EE	Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga: The statistical longest path problem and its application to delay analysis of logical circuits. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 134-139
1998
14	EE	Yusuke Matsunaga: On accelerating pattern matching for technology mapping. ICCAD 1998: 118-122
1996
13	EE	Hiroyuki Higuchi, Yusuke Matsunaga: A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. DAC 1996: 463-466
12	EE	Yusuke Matsunaga: An Efficient Equivalence Checker for Combinational Circuits. DAC 1996: 629-634
1995
11	EE	Hiroyuki Higuchi, Yusuke Matsunaga: Implicit prime compatible generation for minimizing incompletely specified finite state machines. ASP-DAC 1995
1994
10	EE	Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita: LP based cell selection with constraints of timing, area, and power consumption. ICCAD 1994: 378-381
1993
9	EE	Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton: On Computing the Transitive Closure of a State Transition Relation. DAC 1993: 260-265
8	EE	Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga: Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 6-12 (1993)
1991
7	EE	Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita: A Resynthesis Approach for Network Optimization. DAC 1991: 458-463
6		Masahiro Fujita, Yusuke Matsunaga: Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. ICCAD 1991: 560-563
1990
5	EE	Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita: Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. DAC 1990: 284-289
4		Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda: Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD 1990: 38-41
3		Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda: Multi-Level Logic Minimization Across Latch Boundaries. ICCAD 1990: 406-409
1988
2		Fumihiro Maruyama, Taeko Kakuda, Yusuke Matsunaga, Yoriko Minoda, Shuho Sawada, Nobuaki Kawato: co-LODEX: A Cooperative Expert System for Logic design. FGCS 1988: 1299-1306
1986
1	EE	Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki: A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 466-476 (1986)

Coauthor Index

1	Ei Ando	[15]
2	Robert K. Brayton	[9]
3	Kuang-Chien Chen	[7]
4	Hisanori Fujisawa	[8]
5	Masahiro Fujita	[3] [4] [5] [6] [7] [8] [10]
6	Tetsuya Hasebe	[18] [19]
7	Hiroaki Hayashi	[18] [19]
8	Hiroyuki Higuchi	[11] [13] [17]
9	Ryoichi Inanami	[18] [19]
10	Taeko Kakuda	[2]
11	Takeo Kakuda	[3] [4]
12	Yukihiro Kawano	[18] [19]
13	Nobuaki Kawato	[2]
14	Shinji Kimura	[27]
15	Katsumi Kishimoto	[18] [19]
16	Fumihiro Maruyama	[2]
17	Taeko Matsunaga	[23] [25] [27]
18	Patrick C. McGeer	[9]
19	Yoriko Minoda	[2]
20	Kazuaki Murakami	[16] [18] [19] [20]
21	Saburo Muroga	[7]
22	Kenta Nakamura	[18] [19] [20]
23	Toshio Nakata	[15]
24	Tatsuo Ohtsuki	[1]
25	Katsuya Okumura	[18] [19]
26	Tsuyoshi Sadakata	[21] [26] [28]
27	Hitomi Sato	[5]
28	Shuho Sawada	[2]
29	Makoto Sugihara	[16] [18] [19] [20]
30	Kei Suzuki	[1]
31	Masayoshi Tachibana	[1]
32	Taiga Takata	[18] [19] [29] [30]
33	Yutaka Tamiya	[10]
34	Masafumi Yamashita	[15]
35	Yoshihiro Yasue	[5]

Colors in the list of coauthors