Sunil D. Sherlekar

2000
21		Mahesh Mehendale, Sunil D. Sherlekar: Power Reduction Techniques for Portable DSP Applications. VLSI Design 2000: 3
1999
20		Mahesh Mehendale, Sunil D. Sherlekar: Low Power Code Generation of Multiplication-free Linear Transforms. VLSI Design 1999: 42-47
1998
19		Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar: Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. ASP-DAC 1998: 151-156
18	EE	Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh: Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. VLSI Design 1998: 110-115
17	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. VLSI Design 1998: 12-17
16	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Extensions to Programmable DSP architectures for Reduced Power Dissipation. VLSI Design 1998: 37-
15	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Low-power realization of FIR filters on programmable DSPs. IEEE Trans. VLSI Syst. 6(4): 546-553 (1998)
1997
14	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. VLSI Design 1997: 124-129
1996
13	EE	Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar: Optimized Code Generation of Multiplication-free Linear Transforms. DAC 1996: 41-46
12	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Low power realization of FIR filters using multirate architectures. VLSI Design 1996: 370-375
11	EE	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: Monitoring machine based synthesis technique for concurrent error detection in finite state machines. J. Electronic Testing 8(2): 179-201 (1996)
1995
10	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Techniques for low power realization for FIR filters. ASP-DAC 1995
9	EE	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh: Synthesis of multiplier-less FIR filters with minimum number of additions. ICCAD 1995: 668-671
8	EE	B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh: A new methodology for the design of low-cost fail safe circuits and networks. VLSI Design 1995: 355-358
7	EE	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: Concurrent Error Detection Using Monitoring Machines. IEEE Design & Test of Computers 12(3): 24-32 (1995)
1993
6		Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. VLSI Design 1993: 15-20
5		Sunil D. Sherlekar: Export of VLSI Design and CAD: Present and Future. VLSI Design 1993: 264
1992
4	EE	Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran: A Behavioral Fault Simulator for Ideal. IEEE Design & Test of Computers 9(4): 14-21 (1992)
1991
3		Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: A Methodology for Designing Optimal Self-Checking Sequential Circuits. ITC 1991: 283-291
2	EE	Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh: A methodology for the design of SFS/SCD circuits for a class of unordered codes. J. Electronic Testing 2(3): 261-277 (1991)
1988
1	EE	Sunil D. Sherlekar, P. S. Subramanian: Conditionally robust two-pattern tests and CMOS design for testability. IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 325-332 (1988)

Coauthor Index

1	Ajay Khoche	[4]
2	B. Ravi Kishore	[8]
3	Mahesh Mehendale	[9] [10] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
4	Sandeep Pagey	[2] [8]
5	Rubin A. Parekhji	[3] [6] [7] [8] [11]
6	Somdipta Basu Roy	[18]
7	Amit Sinha	[19]
8	P. S. Subramanian	[1]
9	G. Venkatesh	[2] [3] [4] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
10	Raja Venkateswaran	[4]

Colors in the list of coauthors