| 2003 |
|---|
| 8 | EE | Ulrich Seidl,
Klaus Eckl,
Frank M. Johannes:
Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information.
DATE 2003: 10770-10777 |
| 1999 |
|---|
| 7 | EE | Klaus Eckl,
Jean Christophe Madre,
Peter Zepter,
Christian Legl:
A Practical Approach to Multiple-Class Retiming.
DAC 1999: 237-242 |
| 6 | EE | Klaus Eckl,
Christian Legl:
Retiming Sequential Circuits with Multiple Register Classes.
DATE 1999: 650- |
| 5 | EE | Bernd Wurth,
Ulf Schlichtmann,
Klaus Eckl,
Kurt Antreich:
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs.
ACM Trans. Design Autom. Electr. Syst. 4(3): 313-350 (1999) |
| 1998 |
|---|
| 4 | EE | Christian Legl,
Bernd Wurth,
Klaus Eckl:
Computing support-minimal subfunctions during functional decomposition.
IEEE Trans. VLSI Syst. 6(3): 354-363 (1998) |
| 1996 |
|---|
| 3 | EE | Christian Legl,
Bernd Wurth,
Klaus Eckl:
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs.
DAC 1996: 730-733 |
| 2 | | Christian Legl,
Klaus Eckl,
Bernd Wurth:
Performance-Directed Technology-Mapping for LUT-Based FPGAs - What Role Do Decomposition and Covering Play?
FPL 1996: 14-23 |
| 1995 |
|---|
| 1 | EE | Bernd Wurth,
Klaus Eckl,
Kurt Antreich:
Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm.
DAC 1995: 54-59 |
