| 2009 |
|---|
| 41 | EE | Nitin Kataria,
Forrest Brewer,
João Pedro Hespanha,
Timothy Sherwood:
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems.
VLSI Design 2009: 407-412 |
| 2008 |
|---|
| 40 | EE | Greg Hoover,
Forrest Brewer:
Synthesizing Synchronous Elastic Flow Networks.
DATE 2008: 306-311 |
| 39 | EE | Merritt Miller,
Greg Hoover,
Forrest Brewer:
Pulse-mode link for robust, high speed communications.
ISCAS 2008: 3073-3077 |
| 38 | EE | Greg Hoover,
Forrest Brewer,
Chris Gill:
Latency-Insensitive Hardware/Software Interfaces.
MEMOCODE 2008: 71-72 |
| 2007 |
|---|
| 37 | EE | Greg Hoover,
Forrest Brewer,
Timothy Sherwood:
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control.
CASES 2007: 95-102 |
| 36 | EE | Forrest Brewer,
James C. Hoe:
MEMOCODE 2007 Co-Design Contest.
MEMOCODE 2007: 91-94 |
| 2006 |
|---|
| 35 | EE | Greg Hoover,
Forrest Brewer,
Timothy Sherwood:
Extensible control architectures.
CASES 2006: 323-333 |
| 34 | EE | Greg Hoover,
Forrest Brewer,
Timothy Sherwood:
A case study of multi-threading in the embedded space.
CASES 2006: 357-367 |
| 33 | EE | Ryan Kastner,
Wenrui Gong,
Xin Hao,
Forrest Brewer,
Adam Kaplan,
Philip Brisk,
Majid Sarrafzadeh:
Layout driven data communication optimization for high level synthesis.
DATE 2006: 1185-1190 |
| 2005 |
|---|
| 32 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Forrest Brewer:
Structural search for RTL with predicate learning.
DAC 2005: 451-456 |
| 31 | | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Forrest Brewer:
RTL SAT simplification by Boolean and interval arithmetic reasoning.
ICCAD 2005: 297-302 |
| 30 | | Xin Hao,
Forrest Brewer:
Wirelength optimization by optimal block orientation.
ICCAD 2005: 64-70 |
| 29 | | Aravind Vijayakumar,
Forrest Brewer:
Weighted control scheduling.
ICCAD 2005: 777-783 |
| 28 | EE | Greg Hoover,
Forrest Brewer:
PyPBS design and methodologies.
MEMOCODE 2005: 55-64 |
| 2003 |
|---|
| 27 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska,
Forrest Brewer:
Buffer delay change in the presence of power and ground noise.
IEEE Trans. VLSI Syst. 11(3): 461-473 (2003) |
| 2002 |
|---|
| 26 | EE | Lauren Hui Chen,
Malgorzata Marek-Sadowska,
Forrest Brewer:
Coping with buffer delay change due to power and ground noise.
DAC 2002: 860-865 |
| 25 | EE | Forrest Brewer,
Steve Haynal:
Symbolic NFA scheduling of a RISC microprocessor.
IEEE Trans. VLSI Syst. 10(4): 429-434 (2002) |
| 2001 |
|---|
| 24 | EE | Steve Haynal,
Forrest Brewer:
Automata-Based Symbolic Scheduling for Looping DFGs.
IEEE Trans. Computers 50(3): 250-267 (2001) |
| 2000 |
|---|
| 23 | EE | Steve Haynal,
Forrest Brewer:
Representing and Scheduling Looping Behavior Symbolically.
ICCD 2000: 552-555 |
| 22 | EE | Shi-Yu Huang,
Kwang-Ting Cheng,
Kuang-Chien Chen,
Chung-Yang Huang,
Forrest Brewer:
AQUILA: An Equivalence Checking System for Large Sequential Designs.
IEEE Trans. Computers 49(5): 443-464 (2000) |
| 1999 |
|---|
| 21 | EE | Steve Haynal,
Forrest Brewer:
A Model for Scheduling Protocol-Constrained Components and Environments.
DAC 1999: 292-295 |
| 20 | EE | Hien Ha,
Forrest Brewer:
Power and signal integrity improvement in ultra high-speed current mode logic.
ISCAS (1) 1999: 525-528 |
| 1998 |
|---|
| 19 | EE | Steve Haynal,
Forrest Brewer:
Efficient encoding for exact symbolic automata-based scheduling.
ICCAD 1998: 477-481 |
| 1997 |
|---|
| 18 | EE | Chuck Monahan,
Forrest Brewer:
Scheduling and binding bounds for RT-level symbolic execution.
ICCAD 1997: 230-235 |
| 1996 |
|---|
| 17 | EE | Chuck Monahan,
Forrest Brewer:
Concurrent Analysis Techniques for Data Path Timing Optimization.
DAC 1996: 47-50 |
| 16 | EE | Tony Stornetta,
Forrest Brewer:
Implementation of an Efficient Parallel BDD Package.
DAC 1996: 641-644 |
| 15 | EE | Ashok Vittal,
Hein Ha,
Forrest Brewer,
Malgorzata Marek-Sadowska:
Clock skew optimization for ground bounce control.
ICCAD 1996: 395-399 |
| 14 | EE | Ivan P. Radivojevic,
Forrest Brewer:
A new symbolic technique for control-dependent scheduling.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 45-57 (1996) |
| 1995 |
|---|
| 13 | EE | Chuck Monahan,
Forrest Brewer:
Symbolic Modeling and Evaluation of Data Paths.
DAC 1995: 389-394 |
| 12 | EE | Chuck Monahan,
Forrest Brewer:
Symbolic execution of data paths.
Great Lakes Symposium on VLSI 1995: 80-85 |
| 11 | EE | Ivan P. Radivojevic,
Forrest Brewer:
Analysis of conditional resource sharing using a guard-based control representation.
ICCD 1995: 434-445 |
| 1994 |
|---|
| 10 | EE | Ivan P. Radivojevic,
Forrest Brewer:
Incorporating Speculative Execution in Exact Control-Dependent Scheduling.
DAC 1994: 479-484 |
| 9 | EE | Andrew Seawright,
Forrest Brewer:
Clairvoyant: a synthesis system for production-based specification.
IEEE Trans. VLSI Syst. 2(2): 172-185 (1994) |
| 1993 |
|---|
| 8 | EE | Andrew Seawright,
Forrest Brewer:
High-Level Symbolic Construction Technique for High Performance Sequential Synthesis.
DAC 1993: 424-428 |
| 1992 |
|---|
| 7 | EE | Andrew Seawright,
Forrest Brewer:
Synthesis from Production-Based Specifications.
DAC 1992: 194-199 |
| 1991 |
|---|
| 6 | EE | Barry M. Pangrle,
Forrest Brewer,
Donald Lobo,
Andrew Seawright:
Relevant Issues in High-Level Connectivity Synthesis.
DAC 1991: 607-610 |
| 5 | EE | Mario Nemirovsky,
Forrest Brewer,
Roger C. Wood:
DISC: Dynamic Instruction Stream Computer.
MICRO 1991: 163-171 |
| 1990 |
|---|
| 4 | EE | Forrest Brewer,
Barry M. Pangrle,
Andrew Seawright:
Interconnection synthesis with geometric constraints.
MICRO 1990: 158-165 |
| 3 | EE | Forrest Brewer,
Daniel D. Gajski:
Chippe: a system for constraint driven behavioral synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(7): 681-695 (1990) |
| 1987 |
|---|
| 2 | EE | Forrest Brewer,
Daniel Gajski:
Knowledge Based Control in Micro-Architecture Design.
DAC 1987: 203-209 |
| 1986 |
|---|
| 1 | EE | Forrest Brewer,
Daniel Gajski:
An expert-system paradigm for design.
DAC 1986: 62-68 |
