| 2000 |
|---|
| 4 | EE | Rory McInerney,
Kurt Leeper,
Troy Hill,
Heming Chan,
Bulent Basaran,
Lance McQuiddy:
Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor.
ISPD 2000: 99-104 |
| 1999 |
|---|
| 3 | EE | Bulent Basaran,
Kiran Ganesh,
Raymond Y. K. Lau,
Artour Levin,
Miles McCoo,
Srinivasan Rangarajan,
Naresh Sehgal:
GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.
VLSI Design 1999: 448-452 |
| 1996 |
|---|
| 2 | EE | Bulent Basaran,
Rob A. Rutenbar:
An O(n) Algorithm for Transistor Stacking with Performance Constraints.
DAC 1996: 221-226 |
| 1993 |
|---|
| 1 | EE | Bulent Basaran,
Rob A. Rutenbar,
L. Richard Carley:
Latchup-aware placement and parasitic-bounded routing of custom analog cells.
ICCAD 1993: 415-421 |
