| |
| 1997 | ||
|---|---|---|
| 5 | EE | Joe G. Xi, Wayne Wei-Ming Dai: Useful-Skew Clock Routing with Gate Sizing for Low Power Design. VLSI Signal Processing 16(2-3): 163-179 (1997) |
| 1996 | ||
| 4 | EE | Joe G. Xi, Wayne Wei-Ming Dai: Useful-Skew Clock Routing With Gate Sizing for Low Power Design. DAC 1996: 383-388 |
| 3 | EE | Joe G. Xi, Wayne Wei-Ming Dai: Jitter-tolerant clock routing in two-phase synchronous systems. ICCAD 1996: 316-320 |
| 1995 | ||
| 2 | EE | Joe G. Xi, Wayne Wei-Ming Dai: Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution. DAC 1995: 491-496 |
| 1993 | ||
| 1 | EE | Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi: Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models. ICCAD 1993: 628-633 |
| 1 | Wayne Wei-Ming Dai | [1] [2] [3] [4] [5] |
| 2 | Qing Zhu | [1] |