John Lach, Gang Qu, Yehea I. Ismail (Eds.):
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005.
ACM 2005, ISBN 1-59593-057-4 BibTeX
Plenary session
Interconnect
- Noha Mahmoud, Maged Ghoneima, Yehea I. Ismail:
Physical limitations on the bit-rate of on-chip interconnects.
13-19
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- Vasilis F. Pavlidis, Eby G. Friedman:
Interconnect delay minimization through interlayer via placement in 3-D ICs.
20-25
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- Syed M. Alam, Donald E. Troxel, Carl V. Thompson:
Thermal aware cell-based full-chip electromigration reliability analysis.
26-31
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- Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
Accounting for the skin effect during repeater insertion.
32-37
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- Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti:
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.
38-43
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Computer architecture
- Gang Wang, Wenrui Gong, Ryan Kastner:
Instruction scheduling using MAX-MIN ant system optimization.
44-49
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- Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP.
50-55
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- Kimish Patel, Enrico Macii, Massimo Poncino:
Zero clustering: an approach to extend zero compression to instruction caches.
56-59
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- Alireza Hodjat, David Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede:
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.
60-63
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- Shyamkumar Thoziyoor, Jay B. Brockman, Daniel Rinzler:
PIM lite: a multithreaded processor-in-memory prototype.
64-69
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Poster session 1
- Tian Xia, Peilin Song, Hao Zheng:
Characterizing the VCO jitter due to the digital simultaneous switching noise.
70-73
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- Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact minimum-width transistor placement without dual constraint for CMOS cells.
74-77
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- Vishal Suthar, Shantanu Dutt:
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.
78-83
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- Xiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong:
An improved direct boundary element method for substrate coupling resistance extraction.
84-87
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- Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
Generating decision regions in analog measurement spaces.
88-91
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- Ozcan Ozturk, Mahmut T. Kandemir:
Integer linear programming based energy optimization for banked DRAMs.
92-95
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- Amit Jain, David Blaauw:
Slack borrowing in flip-flop based sequential circuits.
96-101
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- Eugene Goldberg:
On equivalence checking and logic synthesis of circuits with a common specification.
102-107
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- Rui Tang, Fengming Zhang, Yong-Bin Kim:
Quantum-dot cellular automata SPICE macro model.
108-111
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- Nirmal Ramalingam, Sanjukta Bhanja:
Causal probabilistic input dependency learning for switching model in VLSI circuits.
112-115
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- Zhiyuan Yan, Dilip V. Sarwate:
Area-efficient two-dimensional architectures for finite field inversion and division.
116-121
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- Jaehong Ko, Wookwan Lee, Soo-Won Kim:
2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design.
122-125
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- Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
The oct-touched tile: a new architecture for shape-based routing.
126-129
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- Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita:
System level design language extensions for timed/untimed digital-analog combined system design.
130-133
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- Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi:
Noise-tolerant high fan-in dynamic CMOS circuit design.
134-137
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- Lei Yang, Cherry Wakayama, C.-J. Richard Shi:
Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer.
138-142
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- Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou:
Improved multilevel routing with redundant via placement for yield and reliability.
143-146
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- Hui Qin, Tsutomu Sasao, Yukihiro Iguchi:
An FPGA design of AES encryption circuit with 128-bit keys.
147-151
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- Eun-Gu Jung, Jeong-Gun Lee, Sang-Hoon Kwak, Kyoung-Sun Jhang, Jeong-A. Lee, Dong-Soo Har:
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.
152-155
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- Rong Liu, Sheqin Dong, Xianlong Hong:
Fixed-outline floorplanning based on common subsequence.
156-159
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- Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa:
Interconnect capacitance extraction for system LCD circuits.
160-163
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- Ying Yang, Zine-Eddine Abid, Wei Wang:
Two-prime RSA immune cryptosystem and its FPGA implementation.
164-167
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- Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural:
A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICs.
168-171
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- Yulei Weng, Alex Doboli:
Digital cell macro-model with regular substrate template and EKV based MOSFET model.
172-175
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Testing
- Vishnu C. Vimjam, Manan Syal, Michael S. Hsiao:
Untestable fault identification through enhanced necessary value assignments.
176-181
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- Stelios Neophytou, Maria K. Michael, Spyros Tragoudas:
Test set enhancement for quality transition faults using function-based methods.
182-187
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- Hamidreza Hashempour, Fabrizio Lombardi:
Two dimensional reordering of functional test data for compression by ATE.
188-192
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- Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour:
Diagnosing multiple transition faults in the absence of timing information.
193-196
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- Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
An EFSM-based approach for functional ATPG.
197-200
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Nano and Emerging Technologies
High-level low power design I
Verification
High-level low power design II
- Ozcan Ozturk, Mahmut T. Kandemir:
Energy management in software-controlled multi-level memory hierarchies.
270-275
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- Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino:
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors.
276-281
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- Gokhan Memik, Mahmut T. Kandemir, Arindam Mallik:
Load elimination for low-power embedded processors.
282-285
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- Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu:
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs.
286-290
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- Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto:
A VLSI array processing oriented fast fourier transform algorithm and hardware implementation.
291-295
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Computer-aided design (CAD)
- Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi:
A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach.
296-301
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- Cristiano Forzan, Davide Pandini:
A complete methodology for an accurate static noise analysis.
302-307
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- Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
A new approach to the use of satisfiability in false path detection.
308-311
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- Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown:
Optimization objectives and models of variation for statistical gate sizing.
313-316
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- Shahin Nazarian, Massoud Pedram, Emre Tuncer:
An empirical study of crosstalk in VDSM technologies.
317-322
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Poster session 2
- Kuan Jen Lin, Shih Hao Huang, Shih Wen Chen:
A hardware/software codesign approach for programmable IO devices.
323-327
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- Srivathsan Krishnamohan, Nihar R. Mahapatra:
Analysis and design of soft-error hardened latches.
328-331
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- Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska:
Clock skew bounds estimation under power supply and process variations.
332-336
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- João Daniel Togni, Renato P. Ribas, Maria Lúcia Blanck Lisbôa, André Inácio Reis:
Tool integration using the web-services approach.
337-340
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- Lin Yuan, Gang Qu, Ankur Srivastava:
VLSI CAD tool protection by birthmarking design solutions.
341-344
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- Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Eugene A. Feinberg:
A continuous time markov decision process based on-chip buffer allocation methodology.
345-348
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- Amir Fijany, Farrokh Vatan, Mohammad Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil:
The G4-FET: a universal and programmable logic gate.
349-352
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- Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin:
Using data compression in an MPSoC architecture for improving performance.
353-356
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- Fei Hu, Vishwani D. Agrawal:
Dual-transition glitch filtering in probabilistic waveform power estimation.
357-360
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- Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri:
SOFTENIT: a methodology for boosting the software content of system-on-chip designs.
361-366
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- Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii:
Low-overhead state-retaining elements for low-leakage MTCMOS design.
367-370
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- Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi:
Enhancing error resilience for reliable compression of VLSI test data.
371-376
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- Prassanna Sithambaram, Alberto Macii, Enrico Macii:
Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.
377-380
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- Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge:
Total leakage optimization strategies for multi-level caches.
381-384
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- Gaurav Gulati, Erik Brunvand:
Design of a cell library for asynchronous microengines.
385-389
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- Amitava Bhaduri, Ranga Vemuri:
Moment-driven coupling-aware routing methodology.
390-395
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- Johannes Grad, James E. Stine:
New algorithms for carry propagation.
396-399
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- Youngsik Kim, Parija Sule, Nazanin Mansouri:
Exploiting PSL standard assertions in a theorem-proving-based verification environment.
400-403
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- Junwei Zhou, Andrew Mason:
Increasing design space of the instruction queue with tag coding.
404-407
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- Ali Bastani, Charles A. Zukowski:
Characterization of monotonic static CMOS gates in a 65nm technology.
408-411
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- Srivathsan Krishnamohan, Nihar R. Mahapatra:
An analysis of the robustness of CMOS delay elements.
412-415
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- Ann Gordon-Ross, Frank Vahid, Nikil Dutt:
A first look at the interplay of code reordering and configurable caches.
416-421
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- Abdallah Merhebi, Otmane Aït Mohamed:
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks.
422-425
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- Soroush Abbaspour, Hanif Fatemi, Massoud Pedram:
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.
426-430
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VLSI circuit design
Routing
Circuit-level low power design
Placement
Copyright © Sat May 16 23:13:51 2009
by Michael Ley (ley@uni-trier.de)
