| |
| 2006 | ||
|---|---|---|
| 2 | EE | Junwei Zhou, Andrew Mason: A two-level hybrid select logic for wide-issue superscalar processors. ISCAS 2006 |
| 2005 | ||
| 1 | EE | Junwei Zhou, Andrew Mason: Increasing design space of the instruction queue with tag coding. ACM Great Lakes Symposium on VLSI 2005: 404-407 |
| 1 | Andrew Mason | [1] [2] |