2009 |
16 | EE | Yifei Luo,
Gang Chen,
Kuan Zhou:
A picosecond TDC architecture for multiphase PLLs.
ACM Great Lakes Symposium on VLSI 2009: 437-440 |
2006 |
15 | EE | Kuan Zhou,
Yifei Luo,
Sizhong Chen,
A. Drake,
John F. McDonald,
Tong Zhang:
Triple-rail MOS current mode logic for high-speed self-timed pipeline applications.
ISCAS 2006 |
2005 |
14 | EE | Kuan Zhou,
John F. McDonald:
Multi-GHz SiGe design methodologies for reconfigurable computing.
ACM Great Lakes Symposium on VLSI 2005: 207-212 |
13 | EE | Jong-Ru Guo,
Chao You,
Kuan Zhou,
Michael Chu,
Peter F. Curran,
Jiedong Diao,
Bryan S. Goda,
Russell P. Kraft,
John F. McDonald:
A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC.
Integration 38(3): 525-540 (2005) |
12 | EE | Kuan Zhou,
Jong-Ru Guo,
Chao You,
John Mayega,
Russell P. Kraft,
T. Zhang,
John F. McDonald,
Bryan S. Goda:
Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques.
Journal of Circuits, Systems, and Computers 14(2): 179-194 (2005) |
11 | EE | Chao You,
Jong-Ru Guo,
Russell P. Kraft,
Michael Chu,
Peter F. Curran,
Kuan Zhou,
Bryan S. Goda,
John F. McDonald:
A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block.
Microprocessors and Microsystems 29(2-3): 121-131 (2005) |
2004 |
10 | EE | Jong-Ru Guo,
Chao You,
Paul F. Curran,
Michael Chu,
Kuan Zhou,
Jiedong Diao,
A. George,
Russell P. Kraft,
John F. McDonald:
The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA.
ACM Great Lakes Symposium on VLSI 2004: 141-144 |
9 | EE | Jong-Ru Guo,
Chao You,
Michael Chu,
Robert W. Heikaus,
Kuan Zhou,
Okan Erdogan,
Jiedong Diao,
Bryan S. Goda,
Russell P. Kraft,
John F. McDonald:
The gigahertz FPGA: design consideration and applications.
FPGA 2004: 248 |
2003 |
8 | EE | John Mayega,
Okan Erdogan,
Paul M. Belemjian,
Kuan Zhou,
John F. McDonald,
Russell P. Kraft:
3D direct vertical interconnect microprocessors test vehicle.
ACM Great Lakes Symposium on VLSI 2003: 141-146 |
7 | EE | Chao You,
Jong-Ru Guo,
Russell P. Kraft,
Kuan Zhou,
Michael Chu,
John F. McDonald:
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology.
ACM Great Lakes Symposium on VLSI 2003: 37-40 |
6 | | Jong-Ru Guo,
Chao You,
Michael Chu,
Kuan Zhou,
Young Uk Yim,
Robert W. Heikaus,
Russell P. Kraft,
John F. McDonald:
A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA.
Engineering of Reconfigurable Systems and Algorithms 2003: 181-187 |
5 | EE | Jong-Ru Guo,
Chao You,
Kuan Zhou,
Bryan S. Goda,
Russell P. Kraft,
John F. McDonald:
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.
FPGA 2003: 145-153 |
4 | EE | Kuan Zhou,
Michael Chu,
Chao You,
Jong-Ru Guo,
Channakeshav,
John Mayega,
John F. McDonald,
Russell P. Kraft,
Bryan S. Goda:
A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.
FPGA 2003: 248 |
3 | EE | Chao You,
Jong-Ru Guo,
Russell P. Kraft,
Michael Chu,
Robert W. Heikaus,
Okan Erdogan,
Peter F. Curran,
Bryan S. Goda,
Kuan Zhou,
John F. McDonald:
Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory.
FPL 2003: 11-20 |
2002 |
2 | EE | Channakeshav,
Kuan Zhou,
Russell P. Kraft,
John F. McDonald:
Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic.
Evolvable Hardware 2002: 60-62 |
1 | EE | Channakeshav,
Kuan Zhou,
Jong-Ru Guo,
Chao You,
Bryan S. Goda,
Russell P. Kraft,
John F. McDonald:
Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques.
FPL 2002: 414-423 |