| 2006 |
|---|
| 5 | EE | Jinjun Xiong,
Vladimir Zolotov,
Natesan Venkateswaran,
Chandu Visweswariah:
Criticality computation in parameterized statistical timing.
DAC 2006: 63-68 |
| 2005 |
|---|
| 4 | EE | Matthew R. Guthaus,
Natesan Venkateswaran,
Vladimir Zolotov,
Dennis Sylvester,
Richard B. Brown:
Optimization objectives and models of variation for statistical gate sizing.
ACM Great Lakes Symposium on VLSI 2005: 313-316 |
| 3 | | Matthew R. Guthaus,
Natesan Venkateswaran,
Chandu Visweswariah,
Vladimir Zolotov:
Gate sizing using incremental parameterized statistical timing analysis.
ICCAD 2005: 1029-1036 |
| 1999 |
|---|
| 2 | EE | Kanad Chakraborty,
Natesan Venkateswaran:
Congestion Mitigation During Placement.
Great Lakes Symposium on VLSI 1999: 228-229 |
| 1996 |
|---|
| 1 | EE | Natesan Venkateswaran,
Dinesh Bhatia:
Clock-Skew Constrained Cell Placement.
VLSI Design 1996: 146-149 |
