| |
| 2005 | ||
|---|---|---|
| 2 | EE | Qingzhou (Ben) Wang, Devang Jariwala, John Lillis: A study of tighter lower bounds in LP relaxation based placement. ACM Great Lakes Symposium on VLSI 2005: 498-502 |
| 1 | EE | Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal: An LP-based methodology for improved timing-driven placement. ASP-DAC 2005: 1139-1143 |
| 1 | Devang Jariwala | [2] |
| 2 | John Lillis | [1] [2] |
| 3 | Shubhankar Sanyal | [1] |