| 2008 |
|---|
| 13 | EE | Masato Inagi,
Yasuhiro Takashima,
Yuichi Nakamura,
Atsushi Takahashi:
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.
ISCAS 2008: 1800-1803 |
| 12 | EE | Yuko Hashizume,
Yasuhiro Takashima,
Yuichi Nakamura:
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation.
IEICE Transactions 91-A(9): 2322-2327 (2008) |
| 2007 |
|---|
| 11 | EE | Tan Yan,
Shuting Li,
Yasuhiro Takashima,
H. Murata:
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks.
ASP-DAC 2007: 268-273 |
| 10 | EE | Kunihiko Yanagibashi,
Yasuhiro Takashima,
Yuichi Nakamura:
A Relocation Method for Circuit Modifications.
IEICE Transactions 90-A(12): 2743-2751 (2007) |
| 9 | EE | Masato Inagi,
Yasuhiro Takashima,
Yuichi Nakamura,
Yoji Kajitani:
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.
IEICE Transactions 90-A(5): 924-931 (2007) |
| 2006 |
|---|
| 8 | EE | Tan Yan,
Qing Dong,
Yasuhiro Takashima,
Yoji Kajitani:
How does partitioning matter for 3D floorplanning?
ACM Great Lakes Symposium on VLSI 2006: 73-78 |
| 7 | EE | Ning Fu,
Shigetoshi Nakatake,
Yasuhiro Takashima,
Yoji Kajitani:
The Oct-Touched Tile: A New Architecture for Shape-Based Routing.
IEICE Transactions 89-A(2): 448-455 (2006) |
| 2005 |
|---|
| 6 | EE | Ning Fu,
Shigetoshi Nakatake,
Yasuhiro Takashima,
Yoji Kajitani:
The oct-touched tile: a new architecture for shape-based routing.
ACM Great Lakes Symposium on VLSI 2005: 126-129 |
| 2004 |
|---|
| 5 | EE | Takashi Nojima,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani:
A device-level placement with multi-directional convex clustering.
ACM Great Lakes Symposium on VLSI 2004: 196-201 |
| 4 | EE | Ning Fu,
Shigetoshi Nakatake,
Yasuhiro Takashima,
Yoji Kajitani:
Abstraction and optimization of consistent floorplanning with pillar block constraints.
ASP-DAC 2004: 19-24 |
| 3 | EE | Takashi Nojima,
Xiaoke Zhu,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani:
Multi-level placement with circuit schema based clustering in analog IC layouts.
ASP-DAC 2004: 406-411 |
| 2 | | Keiji Kida,
Xiaoke Zhu,
Changwen Zhuang,
Yasuhiro Takashima,
Shigetoshi Nakatake:
A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects.
ISCAS (4) 2004: 489-492 |
| 2000 |
|---|
| 1 | EE | Yukiko Kubo,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani:
Self-reforming routing for stochastic search in VLSI interconnection layout.
ASP-DAC 2000: 87-92 |
