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| 2007 | ||
|---|---|---|
| 4 | EE | Hsu-Chun Yen, Chien-Liang Chen: Computing Minimal Elements of Upward-Closed Sets for Petri Nets. ICATPN 2007: 465-483 |
| 3 | EE | Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin: Integration, Verification and Layout of a Complex Multimedia SOC CoRR abs/0710.4667: (2007) |
| 2005 | ||
| 2 | EE | Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen: 1-V 7-mW dual-band fast-locked frequency synthesizer. ACM Great Lakes Symposium on VLSI 2005: 431-435 |
| 1 | EE | Chien-Liang Chen, Jiing-Yuan Lin, Youn-Long Lin: Integration, Verification and Layout of a Complex Multimedia SOC. DATE 2005: 1116-1117 |
| 1 | Charlie Chung-Ping Chen (Chung-Ping Chen) | [2] |
| 2 | Jiing-Yuan Lin | [1] [3] |
| 3 | Youn-Long Lin | [1] [3] |
| 4 | Vikas Sharma | [2] |
| 5 | Hsu-Chun Yen | [4] |