| 2009 |
|---|
| 8 | EE | Vasilis F. Pavlidis,
Giovanni De Micheli:
Power distribution paths in 3-D ICS.
ACM Great Lakes Symposium on VLSI 2009: 263-268 |
| 2008 |
|---|
| 7 | EE | Vasilis F. Pavlidis,
Eby G. Friedman:
Timing-driven via placement heuristics for three-dimensional ICs.
Integration 41(4): 489-508 (2008) |
| 2007 |
|---|
| 6 | EE | Kostas Siozios,
Kostas Sotiriadis,
Vasilis F. Pavlidis,
Dimitrios Soudris:
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.
FPL 2007: 652-655 |
| 5 | EE | Kostas Siozios,
Kostas Sotiriadis,
Vasilis F. Pavlidis,
Dimitrios Soudris:
A software-supported methodology for designing high-performance 3D FPGA architectures.
VLSI-SoC 2007: 54-59 |
| 4 | EE | Vasilis F. Pavlidis,
Eby G. Friedman:
3-D Topologies for Networks-on-Chip.
IEEE Trans. VLSI Syst. 15(10): 1081-1090 (2007) |
| 2006 |
|---|
| 3 | EE | Vasilis F. Pavlidis,
Eby G. Friedman:
Via placement for minimum interconnect delay in three-dimensional (3D) circuits.
ISCAS 2006 |
| 2005 |
|---|
| 2 | EE | Vasilis F. Pavlidis,
Eby G. Friedman:
Interconnect delay minimization through interlayer via placement in 3-D ICs.
ACM Great Lakes Symposium on VLSI 2005: 20-25 |
| 2003 |
|---|
| 1 | EE | Dimitrios Soudris,
K. Sgouropoulos,
Konstantinos Tatas,
Vasilis F. Pavlidis,
Adonios Thanailakis:
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems.
ISCAS (5) 2003: 129-132 |
