Thomas J. Bucelot

List of publications from the DBLP Bibliography Server - FAQ

2005

2 EE Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti: Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI 2005: 38-43

2002

1 EE Gregory P. Rodgers, Isidore G. Bendrihem, Thomas J. Bucelot, Barry D. Burchett, John C. Collins: Infrastructure requirements for a large-scale, multi-site VLSI development project. IBM Journal of Research and Development 46(1): 87-96 (2002)

2005
2	EE	Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti: Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI 2005: 38-43
2002
1	EE	Gregory P. Rodgers, Isidore G. Bendrihem, Thomas J. Bucelot, Barry D. Burchett, John C. Collins: Infrastructure requirements for a large-scale, multi-site VLSI development project. IBM Journal of Research and Development 46(1): 87-96 (2002)

Coauthor Index

1	Isidore G. Bendrihem	[1]
2	Barry D. Burchett	[1]
3	John C. Collins	[1]
4	Giovanni Fiorenza	[2]
5	Mary Yvonne Lanzerotti	[2]
6	Gerald G. Lopez	[2]
7	Phillip Restle (Phillip J. Restle)	[2]
8	Gregory P. Rodgers	[1]