| 2009 |
|---|
| 3 | EE | Remy Chevallier,
Emmanuelle Encrenaz-Tiphène,
Laurent Fribourg,
Weiwen Xu:
Timed verification of the generic architecture of a memory circuit using parametric timed automata.
Formal Methods in System Design 34(1): 59-81 (2009) |
| 2006 |
|---|
| 2 | EE | Remy Chevallier,
Emmanuelle Encrenaz-Tiphène,
Laurent Fribourg,
Weiwen Xu:
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata.
FORMATS 2006: 113-127 |
| 2005 |
|---|
| 1 | EE | Ghiath Al Sammane,
Dominique Borrione,
Remy Chevallier:
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning.
ACM Great Lakes Symposium on VLSI 2005: 260-263 |
