Sean Safarpour

2009
18	EE	Yibin Chen, Sean Safarpour, Andreas G. Veneris, João P. Marques-Silva: Spatial and temporal design debug using partial MaxSAT. ACM Great Lakes Symposium on VLSI 2009: 345-350
17	EE	Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour: Towards automated ECOs in FPGAs. FPGA 2009: 3-12
2007
16	EE	Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian: Trace Compaction using SAT-based Reachability Analysis. ASP-DAC 2007: 932-937
15	EE	Sean Safarpour, Andreas G. Veneris: Abstraction and refinement techniques in automated design debugging. DATE 2007: 1182-1187
14	EE	Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir: Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543
13	EE	Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah: Improved Design Debugging Using Maximum Satisfiability. FMCAD 2007: 13-19
12	EE	Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Smith: A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. ICCAD 2007: 240-245
2006
11	EE	Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan: Efficient SAT-based Boolean matching for FPGA technology mapping. DAC 2006: 466-471
10	EE	Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144
9	EE	Sean Safarpour, Andreas G. Veneris, Rolf Drechsler: Integrating observability don't cares in all-solution SAT solvers. ISCAS 2006
8	EE	Sean Safarpour, Andreas G. Veneris: Abstraction and Refinement Techniques in Automated Design Debugging. MTV 2006: 88-93
2005
7	EE	Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour: Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI 2005: 193-196
6	EE	Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler: Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269
5		Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876
4	EE	Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47
2004
3	EE	Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee: Managing Don't Cares in Boolean Satisfiability. DATE 2004: 260-265
2	EE	Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir: Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209
1	EE	Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith: Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49

Coauthor Index

1	Magdy S. Abadir	[1] [2] [4] [5] [7] [14]
2	Moayad Fahim Ali	[1] [2] [4] [5]
3	Gregg Baeckler	[11]
4	Marco Benedetti	[12]
5	Stephen Dean Brown	[17]
6	Yibin Chen	[18]
7	Rolf Drechsler	[1] [2] [3] [4] [5] [6] [9] [10]
8	Görschwin Fey	[6] [10]
9	Joanne Lee	[3]
10	Mark H. Liffiton	[13]
11	Andrew C. Ling	[17]
12	Jiang Brandon Liu	[7]
13	Hratch Mangassarian	[12] [13] [14] [16]
14	João P. Marques-Silva	[18]
15	Farid N. Najm	[14]
16	Karem A. Sakallah	[13]
17	Freescale Semiconductor	[1]
18	Alexander Smith	[1] [2]
19	Duncan Smith	[12]
20	Andreas G. Veneris	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [18]
21	Richard Yuan	[11]
22	Jianwen Zhu	[17]