| 2008 |
|---|
| 4 | EE | Tay-Jyi Lin,
Shin-Kai Chen,
Yu-Ting Kuo,
Chih-Wei Liu,
Pi-Chen Hsiao:
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications.
Signal Processing Systems 51(3): 209-223 (2008) |
| 2007 |
|---|
| 3 | EE | Pi-Chen Hsiao,
Tay-Jyi Lin,
Chih-Wei Liu,
Chein-Wei Jen:
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP.
ISCAS 2007: 3506-3509 |
| 2005 |
|---|
| 2 | EE | Tay-Jyi Lin,
Chie-Min Chao,
Chia-Hsien Liu,
Pi-Chen Hsiao,
Shin-Kai Chen,
Li-Chun Lin,
Chih-Wei Liu,
Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP.
ACM Great Lakes Symposium on VLSI 2005: 50-55 |
| 1 | EE | Chia-Hsien Liu,
Tay-Jyi Lin,
Chie-Min Chao,
Pi-Chen Hsiao,
Li-Chun Lin,
Shin-Kai Chen,
Chao-Wei Huang,
Chih-Wei Liu,
Chein-Wei Jen:
Hierarchical instruction encoding for VLIW digital signal processors.
ISCAS (4) 2005: 3503-3506 |
