| 2009 |
|---|
| 7 | EE | Kuan Jen Lin,
Yi Tang Chiu,
Shan Chien Fang:
Design Optimization and Automation for Secure Cryptographic Circuits.
VLSI Design 2009: 321-326 |
| 2007 |
|---|
| 6 | EE | Kuan Jen Lin,
Shan Chien Fang,
Shih Hsien Yang,
Cheng Chia Lo:
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware.
DATE 2007: 1265-1270 |
| 5 | EE | Kuan Jen Lin,
Shih Hao Huang,
Shih Wen Chen:
Optimal Allocation of I/O Device Parameters in Hardware and Software Codesign Methodology.
EUC 2007: 541-552 |
| 2006 |
|---|
| 4 | EE | Kuan Jen Lin,
Chuang Hsiang Huang,
Cheng Chia Lo:
Design and Implementation of a Schedulable DMAC on an AMBA-Based SOPC Platform.
APCCAS 2006: 279-282 |
| 3 | EE | Kuan Jen Lin,
Shih Hao Huang,
Shan Chien Fang:
Cooptimization of interface hardware and software for I/O controllers.
DATE 2006: 724-725 |
| 2005 |
|---|
| 2 | EE | Kuan Jen Lin,
Shih Hao Huang,
Shih Wen Chen:
A hardware/software codesign approach for programmable IO devices.
ACM Great Lakes Symposium on VLSI 2005: 323-327 |
| 2004 |
|---|
| 1 | | Kuan Jen Lin,
Shih Wen Chen:
On the formulation of software cost for IO devices.
IASTED Conf. on Software Engineering and Applications 2004: 761-766 |
