2007 |
16 | EE | Masanori Hashimoto,
Takahito Ijichi,
Shingo Takahashi,
Shuji Tsukiyama,
Isao Shirakawa:
Transistor Sizing of LCD Driver Circuit for Technology Migration.
IEICE Transactions 90-A(12): 2712-2717 (2007) |
2006 |
15 | EE | Shuji Tsukiyama,
Masahiko Tomita:
An algorithm for calculating correlation coefficients between Elmore interconnect delays.
ISCAS 2006 |
14 | EE | Shingo Takahashi,
Shuji Tsukiyama,
Masanori Hashimoto,
Isao Shirakawa:
A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays.
IEICE Transactions 89-A(12): 3538-3545 (2006) |
13 | EE | Shuji Tsukiyama,
Masahiko Tomita:
An Algorithm to Calculate Correlation Coefficients between Interconnect Delays for Use in Statistical Timing Analysis.
IEICE Transactions 89-A(2): 535-543 (2006) |
2005 |
12 | EE | Yoshihiro Uchida,
Sadahiro Tani,
Masanori Hashimoto,
Shuji Tsukiyama,
Isao Shirakawa:
Interconnect capacitance extraction for system LCD circuits.
ACM Great Lakes Symposium on VLSI 2005: 160-163 |
2004 |
11 | EE | Shuji Tsukiyama:
Toward stochastic design for digital circuits: statistical static timing analysis.
ASP-DAC 2004: 762-767 |
2002 |
10 | EE | Sadahiro Tani,
Yoshihiro Uchida,
Makoto Furuie,
Shuji Tsukiyama,
BuYeol Lee,
S. Nishi,
Y. Kubota,
Isao Shirakawa,
S. Imai:
Parasitic capacitance modeling for multilevel interconnects.
APCCAS (1) 2002: 59-64 |
2001 |
9 | EE | Shuji Tsukiyama,
Masakazu Tanaka,
Masahiro Fukui:
A statistical static timing analysis considering correlations between delays.
ASP-DAC 2001: 353-358 |
2000 |
8 | EE | Naofumi Tsujii,
Katsutoshi Baba,
Shuji Tsukiyama:
An interconnect topology optimization by a tree transformation.
ASP-DAC 2000: 93-98 |
1996 |
7 | EE | Yu-Liang Wu,
Shuji Tsukiyama,
Malgorzata Marek-Sadowska:
Graph based analysis of 2-D FPGA routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 33-44 (1996) |
1991 |
6 | | Katsunori Tani,
Shuji Tsukiyama,
Shoji Shinoda,
Isao Shirakawa:
On area-efficient drawings of rectangular duals for VLSI floor-plan.
Math. Program. 52: 29-43 (1991) |
1983 |
5 | EE | Shuji Tsukiyama,
Ernest S. Kuh,
Isao Shirakawa:
On the Layering Problem of Multilayer PWB Wiring.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(1): 30-38 (1983) |
4 | EE | Shuji Tsukiyama,
Ikuo Harada,
Masahiro Fukui,
Isao Shirakawa:
A New Global Router for Gate Array LSIsi.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 313-321 (1983) |
1980 |
3 | | Shuji Tsukiyama,
Ernest S. Kuh,
Isao Shirakawa:
On the layering problem of multilayer PWB wiring.
Graph Theory and Algorithms 1980: 20-37 |
2 | EE | Shuji Tsukiyama,
Isao Shirakawa,
Hiroshi Ozaki,
Hiromu Ariyoshi:
An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset.
J. ACM 27(4): 619-632 (1980) |
1977 |
1 | | Shuji Tsukiyama,
Mikio Ide,
Hiromu Ariyoshi,
Isao Shirakawa:
A New Algorithm for Generating All the Maximal Independent Sets.
SIAM J. Comput. 6(3): 505-517 (1977) |