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Shuji Tsukiyama

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2007
16EEMasanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa: Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Transactions 90-A(12): 2712-2717 (2007)
2006
15EEShuji Tsukiyama, Masahiko Tomita: An algorithm for calculating correlation coefficients between Elmore interconnect delays. ISCAS 2006
14EEShingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa: A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Transactions 89-A(12): 3538-3545 (2006)
13EEShuji Tsukiyama, Masahiko Tomita: An Algorithm to Calculate Correlation Coefficients between Interconnect Delays for Use in Statistical Timing Analysis. IEICE Transactions 89-A(2): 535-543 (2006)
2005
12EEYoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa: Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI 2005: 160-163
2004
11EEShuji Tsukiyama: Toward stochastic design for digital circuits: statistical static timing analysis. ASP-DAC 2004: 762-767
2002
10EESadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, S. Nishi, Y. Kubota, Isao Shirakawa, S. Imai: Parasitic capacitance modeling for multilevel interconnects. APCCAS (1) 2002: 59-64
2001
9EEShuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui: A statistical static timing analysis considering correlations between delays. ASP-DAC 2001: 353-358
2000
8EENaofumi Tsujii, Katsutoshi Baba, Shuji Tsukiyama: An interconnect topology optimization by a tree transformation. ASP-DAC 2000: 93-98
1996
7EEYu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska: Graph based analysis of 2-D FPGA routing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 33-44 (1996)
1991
6 Katsunori Tani, Shuji Tsukiyama, Shoji Shinoda, Isao Shirakawa: On area-efficient drawings of rectangular duals for VLSI floor-plan. Math. Program. 52: 29-43 (1991)
1983
5EEShuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa: On the Layering Problem of Multilayer PWB Wiring. IEEE Trans. on CAD of Integrated Circuits and Systems 2(1): 30-38 (1983)
4EEShuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa: A New Global Router for Gate Array LSIsi. IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 313-321 (1983)
1980
3 Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa: On the layering problem of multilayer PWB wiring. Graph Theory and Algorithms 1980: 20-37
2EEShuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki, Hiromu Ariyoshi: An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset. J. ACM 27(4): 619-632 (1980)
1977
1 Shuji Tsukiyama, Mikio Ide, Hiromu Ariyoshi, Isao Shirakawa: A New Algorithm for Generating All the Maximal Independent Sets. SIAM J. Comput. 6(3): 505-517 (1977)

Coauthor Index

1Hiromu Ariyoshi [1] [2]
2Katsutoshi Baba [8]
3Masahiro Fukui [4] [9]
4Makoto Furuie [10]
5Ikuo Harada [4]
6Masanori Hashimoto [12] [14] [16]
7Mikio Ide [1]
8Takahito Ijichi [16]
9S. Imai [10]
10Y. Kubota [10]
11Ernest S. Kuh [3] [5]
12BuYeol Lee [10]
13Malgorzata Marek-Sadowska [7]
14S. Nishi [10]
15Hiroshi Ozaki [2]
16Shoji Shinoda [6]
17Isao Shirakawa [1] [2] [3] [4] [5] [6] [10] [12] [14] [16]
18Shingo Takahashi [14] [16]
19Masakazu Tanaka [9]
20Katsunori Tani [6]
21Sadahiro Tani [10] [12]
22Masahiko Tomita [13] [15]
23Naofumi Tsujii [8]
24Yoshihiro Uchida [10] [12]
25Yu-Liang Wu (David Yu-Liang Wu) [7]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)