| 2005 |
|---|
| 9 | EE | Sankalp Kallakuri,
Nattawut Thepayasuwan,
Alex Doboli,
Eugene A. Feinberg:
A continuous time markov decision process based on-chip buffer allocation methodology.
ACM Great Lakes Symposium on VLSI 2005: 345-348 |
| 8 | EE | Sankalp Kallakuri,
Nattawut Thepayasuwan,
Alex Doboli,
Simona Doboli:
Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies.
ISCAS (2) 2005: 1044-1047 |
| 7 | EE | Nattawut Thepayasuwan,
Alex Doboli:
Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed.
IEEE Trans. VLSI Syst. 13(5): 525-538 (2005) |
| 2004 |
|---|
| 6 | EE | Nattawut Thepayasuwan,
Alex Doboli:
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip.
DATE 2004: 108-113 |
| 5 | EE | Nattawut Thepayasuwan,
Alex Doboli:
Hardware-Software Co-Design of Resource Constrained Systems on a Chip.
ICDCS Workshops 2004: 818-823 |
| 4 | EE | Nattawut Thepayasuwan,
Alex Doboli:
OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip.
ISVLSI 2004: 264-265 |
| 2003 |
|---|
| 3 | EE | Nattawut Thepayasuwan,
Vaishali Damle,
Alex Doboli:
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip.
ICCD 2003: 126-133 |
| 2 | EE | Nattawut Thepayasuwan,
Hua Tang,
Alex Doboli:
An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications.
ISCAS (5) 2003: 629-632 |
| 2002 |
|---|
| 1 | | Nattawut Thepayasuwan,
Alex Doboli:
A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints.
IWLS 2002: 57-60 |
