2006 |
26 | EE | Zhiyuan Yan,
Dilip V. Sarwate,
Zhongzhi Liu:
Erratum to: "High-speed systolic architectures for finite field inversion" [Integration 38(3) (2005) 383-398].
Integration 39(4): 474-476 (2006) |
2005 |
25 | | Tor Helleseth,
Dilip V. Sarwate,
Hong-Yeop Song,
Kyeongcheol Yang:
Sequences and Their Applications - SETA 2004, Third International Conference, Seoul, Korea, October 24-28, 2004, Revised Selected Papers
Springer 2005 |
24 | EE | Zhiyuan Yan,
Dilip V. Sarwate:
Area-efficient two-dimensional architectures for finite field inversion and division.
ACM Great Lakes Symposium on VLSI 2005: 116-121 |
23 | EE | Zhiyuan Yan,
Dilip V. Sarwate,
Zhongzhi Liu:
Area-efficient systolic architectures for inversions over GF(2/sup m/).
ISCAS (6) 2005: 5838-5841 |
22 | EE | Dilip V. Sarwate:
Comments on "Lower bounds on the Hamming auto- and cross correlations of frequency-hopping sequences" by D. Peng and P. Fan.
IEEE Transactions on Information Theory 51(4): 1615- (2005) |
21 | EE | Zhiyuan Yan,
Dilip V. Sarwate,
Zhongzhi Liu:
High-speed systolic architectures for finite field inversion.
Integration 38(3): 383-398 (2005) |
2004 |
20 | EE | Zhiyuan Yan,
Dilip V. Sarwate:
High-speed systolic architectures for finite field inversion and division.
ACM Great Lakes Symposium on VLSI 2004: 462-465 |
19 | EE | Zhiyuan Yan,
Dilip V. Sarwate:
Universal Reed-Solomon decoders based on the Berlekamp-Massey algorithm.
ACM Great Lakes Symposium on VLSI 2004: 51-56 |
2003 |
18 | EE | Zhiyuan Yan,
Dilip V. Sarwate:
New Systolic Architectures for Inversion and Division in GF(2^m).
IEEE Trans. Computers 52(11): 1514-1519 (2003) |
17 | EE | Zukui Song,
Dilip V. Sarwate:
The frequency spectrum of pulse width modulated signals.
Signal Processing 83(10): 2227-2258 (2003) |
2002 |
16 | EE | Zhiyuan Yan,
Dilip V. Sarwate:
Systolic architectures for finite field inversion and division.
ISCAS (5) 2002: 789-792 |
2001 |
15 | EE | Dilip V. Sarwate,
Naresh R. Shanbhag:
High-speed architectures for Reed-Solomon decoders.
IEEE Trans. VLSI Syst. 9(5): 641-655 (2001) |
1994 |
14 | | M. Srinivasan,
Dilip V. Sarwate:
Malfunction in the Peterson-Gorenstein- Zierler decoder.
IEEE Transactions on Information Theory 40(5): 1649- (1994) |
1990 |
13 | | Kapil K. Chawla,
Dilip V. Sarwate:
Upper bounds on the probability of error for M-ary orthogonal signaling in white Gaussian noise.
IEEE Transactions on Information Theory 36(3): 627- (1990) |
12 | | Arvind Krishna,
Dilip V. Sarwate:
Pseudocyclic maximum- distance-separable codes.
IEEE Transactions on Information Theory 36(4): 880- (1990) |
11 | | Dilip V. Sarwate,
Robert D. Morrison:
Decoder malfunction in BCH decoders.
IEEE Transactions on Information Theory 36(4): 884- (1990) |
1988 |
10 | | Dilip V. Sarwate:
Computation of Cyclic Redundancy Checks via Table Look-Up.
Commun. ACM 31(8): 1008-1013 (1988) |
1984 |
9 | | S. M. Krone,
Dilip V. Sarwate:
Quadriphase sequences for spread-spectrum multiple-access communication.
IEEE Transactions on Information Theory 30(3): 520-528 (1984) |
8 | | Dilip V. Sarwate:
In Memoriam: Robert Tienwen Chien (1931-1983).
IEEE Transactions on Information Theory 30(4): 583-586 (1984) |
7 | | Dilip V. Sarwate:
An upper bound on the aperiodic autocorrelation function for a maximal-length sequence.
IEEE Transactions on Information Theory 30(4): 685- (1984) |
1983 |
6 | EE | Dilip V. Sarwate:
A Note on ``A Note on Multiple Error Detection in ASCII Numeric Data Communication''
J. ACM 30(1): 33-35 (1983) |
1981 |
5 | | Robert J. McEliece,
Dilip V. Sarwate:
On Sharing Secrets and Reed-Solomon Codes.
Commun. ACM 24(9): 583-584 (1981) |
1980 |
4 | | Dilip V. Sarwate:
A Note on Universal Classes of Hash Functions.
Inf. Process. Lett. 10(1): 41-45 (1980) |
1979 |
3 | | Daniel S. Hirschberg,
Ashok K. Chandra,
Dilip V. Sarwate:
Computing Connected Components on Parallel Computers.
Commun. ACM 22(8): 461-464 (1979) |
1978 |
2 | | Dilip V. Sarwate:
Semi-Fast Fourier Transforms over GF(2m).
IEEE Trans. Computers 27(3): 283-285 (1978) |
1 | | Franco P. Preparata,
Dilip V. Sarwate:
An Improved Parallel Processor Bound in Fast Matrix Inversion.
Inf. Process. Lett. 7(3): 148-150 (1978) |