| 2001 |
|---|
| 11 | EE | I-Min Liu,
Hung-Ming Chen,
Tan-Li Chou,
Adnan Aziz,
D. F. Wong:
Integrated power supply planning and floorplanning.
ASP-DAC 2001: 589-594 |
| 2000 |
|---|
| 10 | EE | I-Min Liu,
Tan-Li Chou,
Adnan Aziz,
D. F. Wong:
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.
ISPD 2000: 33-38 |
| 9 | EE | Hendrawan Soeleman,
Kaushik Roy,
Tan-Li Chou:
Estimating Circuit Activity in Combinational CMOS Digital Circuits.
IEEE Design & Test of Computers 17(2): 112-119 (2000) |
| 1998 |
|---|
| 8 | EE | Zhanping Chen,
Kaushik Roy,
Tan-Li Chou:
Efficient statistical approach to estimate power considering uncertain properties of primary inputs.
IEEE Trans. VLSI Syst. 6(3): 484-492 (1998) |
| 1997 |
|---|
| 7 | EE | Zhanping Chen,
Kaushik Roy,
Tan-Li Chou:
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.
ICCAD 1997: 40-44 |
| 6 | EE | P. Patil,
Tan-Li Chou,
Kaushik Roy,
R. Roy:
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique.
VLSI Design 1997: 179-184 |
| 1996 |
|---|
| 5 | EE | Tan-Li Chou,
Kaushik Roy:
Accurate power estimation of CMOS sequential circuits.
IEEE Trans. VLSI Syst. 4(3): 369-380 (1996) |
| 4 | EE | Tan-Li Chou,
Kaushik Roy:
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1257-1265 (1996) |
| 1995 |
|---|
| 3 | EE | Tan-Li Chou,
Kaushik Roy:
Statistical estimation of sequential circuit activity.
ICCAD 1995: 34-37 |
| 2 | EE | Tan-Li Chou,
Kaushik Roy:
Estimation of sequential circuit activity considering spatial and temporal correlations.
ICCD 1995: 577- |
| 1994 |
|---|
| 1 | EE | Tan-Li Chou,
Kaushik Roy,
Sharat Prasad:
Estimation of circuit activity considering signal correlations and simultaneous switching.
ICCAD 1994: 300-303 |
