| 2001 |
|---|
| 10 | EE | Amir H. Farrahi,
Chunhong Chen,
Ankur Srivastava,
Gustavo E. Téllez,
Majid Sarrafzadeh:
Activity-driven clock design.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 705-714 (2001) |
| 2000 |
|---|
| 9 | EE | Amir H. Farrahi,
David J. Hathaway,
Maogang Wang,
Majid Sarrafzadeh:
Quality of EDA CAD Tools: Definitions, Metrics and Directions.
ISQED 2000: 395-406 |
| 8 | EE | Amir H. Farrahi:
Estimation and removal or routing congestion (discussion session).
SLIP 2000: 149 |
| 7 | | Wei-Liang Lin,
Amir H. Farrahi,
Majid Sarrafzadeh:
On the Power of Logic Resynthesis.
SIAM J. Comput. 29(4): 1257-1289 (2000) |
| 1999 |
|---|
| 6 | EE | Amir H. Farrahi,
D. T. Lee,
Majid Sarrafzadeh:
Two-Way and Multiway Partitioning of a Set of Intervals for Clique-Width Maximization.
Algorithmica 23(3): 187-210 (1999) |
| 1995 |
|---|
| 5 | EE | Amir H. Farrahi,
Gustavo E. Téllez,
Majid Sarrafzadeh:
Memory Segmentation to Exploit Sleep Mode Operation.
DAC 1995: 36-41 |
| 4 | EE | Amir H. Farrahi,
Majid Sarrafzadeh:
System partitioning to maximize sleep time.
ICCAD 1995: 452-455 |
| 3 | EE | Gustavo E. Téllez,
Amir H. Farrahi,
Majid Sarrafzadeh:
Activity-driven clock design for low power circuits.
ICCAD 1995: 62-65 |
| 1994 |
|---|
| 2 | | Amir H. Farrahi,
Majid Sarrafzadeh:
FPGA Technology Mapping for Power Minimization.
FPL 1994: 66-77 |
| 1 | EE | Amir H. Farrahi,
Majid Sarrafzadeh:
Complexity of the lookup-table minimization problem for FPGA technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(11): 1319-1332 (1994) |
