| 2004 |
|---|
| 8 | EE | D. Zhou,
V. Lo:
Cluster Computing on the Fly: resource discovery in a cycle sharing peer-to-peer system.
CCGRID 2004: 66-73 |
| 2001 |
|---|
| 7 | EE | D. Zhou,
Wei Li,
W. Cai,
N. Guo:
An efficient balanced truncation realization algorithm for interconnect model order reduction.
ISCAS (5) 2001: 383-386 |
| 6 | EE | W. Li,
D. Zhou,
H. Kim,
X. Zeng:
Automatic clock tree design with IPs in the system.
ISCAS (5) 2001: 387-390 |
| 5 | EE | X. Zeng,
D. Zhou:
Design of GHz VLSI clock distribution circuit.
ISCAS (5) 2001: 391-394 |
| 1999 |
|---|
| 4 | EE | X. Zeng,
J. Guan,
W. Q. Zhao,
P. S. Tang,
D. Zhou:
A constraint-based placement refinement method for CMOS analog cell layout.
ISCAS (6) 1999: 408-411 |
| 3 | EE | X. Zeng,
D. Zhou,
Wei Li:
Buffer insertion for clock delay and skew minimization.
ISPD 1999: 36-41 |
| 1997 |
|---|
| 2 | EE | D. Zhou,
X. Y. Liu:
Minimization of chip size and power consumption of high-speed VLSI buffers.
ISPD 1997: 186-191 |
| 1995 |
|---|
| 1 | EE | D. Zhou,
N. Chen,
W. Cai:
A fast wavelet collocation method for high-speed VLSI circuit simulation.
ICCAD 1995: 115-122 |
