| 2005 |
|---|
| 13 | EE | Takayuki Suyama,
Makoto Yokoo:
Strategy/false-name proof protocols for combinatorial multi-attribute procurement auction: handling arbitrary utility of the buyer.
AAMAS 2005: 1195-1196 |
| 12 | EE | Takayuki Suyama,
Makoto Yokoo:
Strategy/False-Name Proof Protocols for Combinatorial Multi-attribute Procurement Auction: Handling Arbitrary Utility of the Buyer.
WINE 2005: 278-287 |
| 11 | EE | Takayuki Suyama,
Makoto Yokoo:
Strategy/False-name Proof Protocols for Combinatorial Multi-Attribute Procurement Auction.
Autonomous Agents and Multi-Agent Systems 11(1): 7-21 (2005) |
| 2004 |
|---|
| 10 | EE | Takayuki Suyama,
Makoto Yokoo:
Strategy/False-name Proof Protocols for Combinatorial Multi-Attribute Procurement Auction.
AAMAS 2004: 160-167 |
| 2001 |
|---|
| 9 | EE | Takayuki Suyama,
Makoto Yokoo,
Hiroshi Sawada,
Akira Nagoya:
Solving satisfiability problems using reconfigurable computing.
IEEE Trans. VLSI Syst. 9(1): 109-116 (2001) |
| 1999 |
|---|
| 8 | EE | Hidehisa Nagano,
Takayuki Suyama,
Akira Nagoya:
Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach.
ASP-DAC 1999: 161-164 |
| 7 | | Takayuki Suyama,
Makoto Yokoo,
Akira Nagoya:
Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation.
CP 1999: 434-445 |
| 6 | | Takayuki Suyama,
Makoto Yokoo,
Akira Nagoya:
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic.
IPPS/SPDP Workshops 1999: 709-711 |
| 1998 |
|---|
| 5 | EE | Hidehisa Nagano,
Takayuki Suyama,
Akira Nagoya:
Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract).
FPGA 1998: 261 |
| 1996 |
|---|
| 4 | | Makoto Yokoo,
Takayuki Suyama,
Hiroshi Sawada:
Solving Satisfiability Problems Using Field Programmable Gate Arrays: First Results.
CP 1996: 497-509 |
| 3 | | Takayuki Suyama,
Makoto Yokoo,
Hiroshi Sawada:
Solving Satisfiability Problems on FPGAs.
FPL 1996: 136-145 |
| 2 | EE | Takayuki Suyama,
Hiroshi Sawada,
Akira Nagoya:
LUT-based FPGA Technology Mapping using Permissible Functions.
VLSI Design 1996: 215-218 |
| 1995 |
|---|
| 1 | EE | Hiroshi Sawada,
Takayuki Suyama,
Akira Nagoya:
Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization.
ICCAD 1995: 353-358 |
