1997 |
8 | EE | Xianlong Hong,
Tianxiong Xue,
Jin Huang,
Chung-Kuan Cheng,
Ernest S. Kuh:
TIGER: an efficient timing-driven global router for gate array and standard cell layout design.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1323-1331 (1997) |
7 | EE | Tianxiong Xue,
Ernest S. Kuh,
Dongsheng Wang:
Post global routing crosstalk synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1418-1430 (1997) |
1996 |
6 | EE | Tianxiong Xue,
Ernest S. Kuh,
Dongsheng Wang:
Post global routing crosstalk risk estimation and reduction.
ICCAD 1996: 302-309 |
5 | EE | Qingjian Yu,
Ernest S. Kuh,
Tianxiong Xue:
Moment models of general transmission lines with application to interconnect analysis and optimization.
IEEE Trans. VLSI Syst. 4(4): 477-494 (1996) |
1995 |
4 | EE | Tianxiong Xue,
Ernest S. Kuh:
Post routing performance optimization via tapered link insertion and wiresizing.
EURO-DAC 1995: 74-79 |
3 | EE | Tianxiong Xue,
Ernest S. Kuh:
Post routing performance optimization via multi-link insertion and non-uniform wiresizing.
ICCAD 1995: 575-580 |
1993 |
2 | EE | Xianlong Hong,
Tianxiong Xue,
Ernest S. Kuh,
Chung-Kuan Cheng,
Jin Huang:
Performance-Driven Steiner Tree Algorithm for Global Routing.
DAC 1993: 177-181 |
1 | | Tianxiong Xue,
Takashi Fujii,
Ernest S. Kuh:
A new performance-driven global routing algorithm for gate array.
VLSI 1993: 321-330 |