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Tianxiong Xue

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1997
8EEXianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh: TIGER: an efficient timing-driven global router for gate array and standard cell layout design. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1323-1331 (1997)
7EETianxiong Xue, Ernest S. Kuh, Dongsheng Wang: Post global routing crosstalk synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1418-1430 (1997)
1996
6EETianxiong Xue, Ernest S. Kuh, Dongsheng Wang: Post global routing crosstalk risk estimation and reduction. ICCAD 1996: 302-309
5EEQingjian Yu, Ernest S. Kuh, Tianxiong Xue: Moment models of general transmission lines with application to interconnect analysis and optimization. IEEE Trans. VLSI Syst. 4(4): 477-494 (1996)
1995
4EETianxiong Xue, Ernest S. Kuh: Post routing performance optimization via tapered link insertion and wiresizing. EURO-DAC 1995: 74-79
3EETianxiong Xue, Ernest S. Kuh: Post routing performance optimization via multi-link insertion and non-uniform wiresizing. ICCAD 1995: 575-580
1993
2EEXianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang: Performance-Driven Steiner Tree Algorithm for Global Routing. DAC 1993: 177-181
1 Tianxiong Xue, Takashi Fujii, Ernest S. Kuh: A new performance-driven global routing algorithm for gate array. VLSI 1993: 321-330

Coauthor Index

1Chung-Kuan Cheng [2] [8]
2Takashi Fujii [1]
3Xianlong Hong [2] [8]
4Jin Huang [2] [8]
5Ernest S. Kuh [1] [2] [3] [4] [5] [6] [7] [8]
6Dongsheng Wang [6] [7]
7Qingjian Yu [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)