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Hirendu Vaishnav

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2001
8EEHirendu Vaishnav, Massoud Pedram: Alphabetic trees-theory and applications in layout-driven logicsynthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 58-69 (2001)
1999
7EEHirendu Vaishnav, Massoud Pedram: Delay-optimal clustering targeting low-power VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 799-812 (1999)
1997
6 Hirendu Vaishnav, Chi-Keung Lee, Massoud Pedram: Post Layout Speed-up by Event Elimination. ICCD 1997: 211-216
5EEMassoud Pedram, Hirendu Vaishnav: Power Optimization in VLSI Layout: A Survey. VLSI Signal Processing 15(3): 221-232 (1997)
1995
4EEHirendu Vaishnav, Massoud Pedram: Minimizing the Routing Cost During Logic Extraction. DAC 1995: 70-75
3EEHirendu Vaishnav, Massoud Pedram: Delay optimal partitioning targeting low power VLSI circuits. ICCAD 1995: 638-643
2EEHirendu Vaishnav, Massoud Pedram: Logic extraction based on normalized netlengths. ICCD 1995: 658-663
1993
1EEHirendu Vaishnav, Massoud Pedram: Routability-Driven Fanout Optimization. DAC 1993: 230-235

Coauthor Index

1Chi-Keung Lee [6]
2Massoud Pedram [1] [2] [3] [4] [5] [6] [7] [8]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)