| |
| 2001 | ||
|---|---|---|
| 8 | EE | Hirendu Vaishnav, Massoud Pedram: Alphabetic trees-theory and applications in layout-driven logicsynthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 58-69 (2001) |
| 1999 | ||
| 7 | EE | Hirendu Vaishnav, Massoud Pedram: Delay-optimal clustering targeting low-power VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 799-812 (1999) |
| 1997 | ||
| 6 | Hirendu Vaishnav, Chi-Keung Lee, Massoud Pedram: Post Layout Speed-up by Event Elimination. ICCD 1997: 211-216 | |
| 5 | EE | Massoud Pedram, Hirendu Vaishnav: Power Optimization in VLSI Layout: A Survey. VLSI Signal Processing 15(3): 221-232 (1997) |
| 1995 | ||
| 4 | EE | Hirendu Vaishnav, Massoud Pedram: Minimizing the Routing Cost During Logic Extraction. DAC 1995: 70-75 |
| 3 | EE | Hirendu Vaishnav, Massoud Pedram: Delay optimal partitioning targeting low power VLSI circuits. ICCAD 1995: 638-643 |
| 2 | EE | Hirendu Vaishnav, Massoud Pedram: Logic extraction based on normalized netlengths. ICCD 1995: 658-663 |
| 1993 | ||
| 1 | EE | Hirendu Vaishnav, Massoud Pedram: Routability-Driven Fanout Optimization. DAC 1993: 230-235 |
| 1 | Chi-Keung Lee | [6] |
| 2 | Massoud Pedram | [1] [2] [3] [4] [5] [6] [7] [8] |