Kiyoharu Hamaguchi

2008
17	EE	Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara: Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic. ATVA 2008: 318-331
2007
16	EE	Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara: Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints. IEICE Transactions 90-A(12): 2778-2789 (2007)
2006
15	EE	Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara: Expressive Power of Quantum Pushdown Automata with Classical Stack Operations under the Perfect-Soundness Condition. IEICE Transactions 89-D(3): 1120-1127 (2006)
2005
14	EE	Y. Kakiuchi, A. Kitajima, Kiyoharu Hamaguchi, Toshinobu Kashiwabara: Automatic monitor generation from regular expression based specifications for module interface verification. ISCAS (4) 2005: 3555-3558
2004
13	EE	Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara: Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas. ATVA 2004: 108-119
2000
12	EE	Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara: Ordered Quantum Branching Programs Are More Powerful than Ordered Probabilistic Branching Programs under a Bounded-Width Restriction. COCOON 2000: 467-476
11	EE	Kiyoharu Hamaguchi, Hidekazu Urushihara, Toshinobu Kashiwabara: Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs. FMCAD 2000: 455-469
1997
10		Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi: Another Look at LTL Model Checking. Formal Methods in System Design 10(1): 47-71 (1997)
1995
9	EE	Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima: Efficient construction of binary moment diagrams for verifying arithmetic circuits. ICCAD 1995: 78-82
1994
8		Edmund M. Clarke, Orna Grumberg, Kiyoharu Hamaguchi: Another Look at LTL Model Checking. CAV 1994: 415-427
1993
7		Seiichiro Tani, Kiyoharu Hamaguchi, Shuzo Yajima: The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams. ISAAC 1993: 389-398
1992
6		Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima: Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic. CAV 1992: 206-219
5		Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima: Infinity-Regular Temporal Logic and its Model Checking Problem. Theor. Comput. Sci. 103(2): 191-204 (1992)
1991
4		Hiromi Hiraishi, Kiyoharu Hamaguchi, Hiroyuki Ochi, Shuzo Yajima: Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification. CAV 1991: 214-224
3		Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima: Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic. CAV 1991: 410-420
1990
2		Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima: Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity. CAV 1990: 253-262
1		Hiromi Hiraishi, Shintaro Meki, Kiyoharu Hamaguchi: Vectorized Model Checking for Computation Tree Logic. CAV 1990: 44-53

Coauthor Index

1	Edmund M. Clarke	[8] [10]
2	Orna Grumberg	[8] [10]
3	Hiromi Hiraishi	[1] [2] [3] [4] [5] [6]
4	Y. Kakiuchi	[14]
5	Toshinobu Kashiwabara	[11] [12] [13] [14] [15] [16] [17]
6	A. Kitajima	[14]
7	Hiroaki Kozawa	[16]
8	Shintaro Meki	[1]
9	Akihito Morita	[9]
10	Atsushi Moritomo	[13]
11	Masaki Nakanishi	[12] [15]
12	Hiroyuki Ochi	[4]
13	Hiroaki Shimizu	[17]
14	Seiichiro Tani	[7]
15	Hidekazu Urushihara	[11]
16	Shuzo Yajima	[2] [3] [4] [5] [6] [7] [9]