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Weitong Chuang

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2000
7EESachin S. Sapatnekar, Weitong Chuang: Power-delay optimizations in gate sizing. ACM Trans. Design Autom. Electr. Syst. 5(1): 98-114 (2000)
1995
6EESachin S. Sapatnekar, Weitong Chuang: Power vs. delay in gate sizing: conflicting objectives? ICCAD 1995: 463-466
5EEWeitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj: Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 308-320 (1995)
4EETerry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs: Circuit-level dictionaries of CMOS bridging faults. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 596-603 (1995)
1994
3EEWeitong Chuang, Ibrahim N. Hajj: Delay and area optimization for compact placement by gate resizing and relocation. ICCAD 1994: 145-148
1993
2EEWeitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj: A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD 1993: 220-223
1 Weitong Chuang, Ibrahim N. Hajj: Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection. ISCAS 1993: 1503-1506

Coauthor Index

1W. Kent Fuchs [4]
2Ibrahim N. Hajj [1] [2] [3] [4] [5]
3Terry Lee [4]
4Sachin S. Sapatnekar [2] [5] [6] [7]

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