| |
| 2007 | ||
|---|---|---|
| 5 | EE | Manoj Gupta, Fermín Sánchez, Josep Llosa: Merge Logic for Clustered Multithreaded VLIW Processors. DSD 2007: 353-360 |
| 4 | EE | Manoj Gupta, Fermín Sánchez, Josep Llosa: Cluster-level simultaneous multithreading for VLIW processors. ICCD 2007: 121-128 |
| 1998 | ||
| 3 | EE | Fermín Sánchez, Jordi Cortadella: Reducing Register Pressure in Software Pipelining. J. Inf. Sci. Eng. 14(1): 265-279 (1998) |
| 1996 | ||
| 2 | Fermín Sánchez, Jordi Cortadella: RESIS: A New Methodology for Register Optimization in Software Pipelining. Euro-Par, Vol. II 1996: 824-832 | |
| 1995 | ||
| 1 | EE | Fermín Sánchez: Time-Constrained Loop Pipelining. ICCAD 1995: 592 |
| 1 | Jordi Cortadella | [2] [3] |
| 2 | Manoj Gupta | [4] [5] |
| 3 | Josep Llosa | [4] [5] |