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Guangqiu Chen

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1996
2EEGuangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru: Timing and Power Optimization by Gate Sizing Considering False Paths. Great Lakes Symposium on VLSI 1996: 154-
1995
1EEGuangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru: An iterative gate sizing approach with accurate delay evaluation. ICCAD 1995: 422-427

Coauthor Index

1Hidetoshi Onodera [1] [2]
2Keikichi Tamaru [1] [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)