Carl-Johan H. Seger

2007
43	EE	Sara Adams, Magnus Björk, Thomas F. Melham, Carl-Johan H. Seger: Automatic Abstraction in Symbolic Trajectory Evaluation. FMCAD 2007: 127-135
2005
42	EE	Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark Aagaard, Clark Barrett, Don Syme: An industrially effective environment for formal hardware verification. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1381-1405 (2005)
2004
41	EE	Jin Yang, Carl-Johan H. Seger: Compositional Specification and Model Checking in GSTE. CAV 2004: 216-228
2003
40	EE	Jin Yang, Carl-Johan H. Seger: Introduction to generalized symbolic trajectory evaluation. IEEE Trans. VLSI Syst. 11(3): 345-353 (2003)
2002
39	EE	Jin Yang, Carl-Johan H. Seger: Generalized Symbolic Trajectory Evaluation - Abstraction in Action. FMCAD 2002: 70-87
2001
38	EE	John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss: CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143
37		Jin Yang, Carl-Johan H. Seger: Introduction to Generalized Symbolic Trajectory Evaluation. ICCD 2001: 360-367
36	EE	Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark Aagaard, Thomas F. Melham: Practical Formal Verification in Microprocessor Design. IEEE Design & Test of Computers 18(4): 16-25 (2001)
2000
35		Carl-Johan H. Seger: Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice. CADE 2000: 235
34	EE	Mark Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger: Formal verification of iterative algorithms in microprocessors. DAC 2000: 201-206
33	EE	Mark Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger: A Methodology for Large-Scale Hardware Verification. FMCAD 2000: 263-282
32	EE	Carl-Johan H. Seger: Combining functional programming and hardware verification (abstract of invited talk). ICFP 2000: 244
1999
31	EE	Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger: Parametric Representations of Boolean Constraints. DAC 1999: 402-407
30	EE	Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger: Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving. TPHOLs 1999: 323-340
29	EE	Scott Hazelhurst, Carl-Johan H. Seger: Model Checking Lattices: Using and reasoning about information orders for abstraction. Logic Journal of the IGPL 7(3): 375-411 (1999)
1998
28	EE	Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger: Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. DAC 1998: 538-541
27	EE	Carl-Johan H. Seger: Formal Methods in CAD from an Industrial Perspective (abstract). FMCAD 1998: 203
26		Carl-Johan H. Seger: From lattices to practical formal hardware verification. PROCOMET 1998: 3-4
1997
25		Scott Hazelhurst, Carl-Johan H. Seger: Symbolic Trajectory Evaluation. Formal Hardware Verification 1997: 3-78
1996
24		Robert B. Jones, Carl-Johan H. Seger, David L. Dill: Self-Consistency Checking. FMCAD 1996: 159-171
1995
23	EE	Mark Aagaard, Carl-Johan H. Seger: The formal verification of a pipelined double-precision IEEE floating-point multiplier. ICCAD 1995: 7-10
22		Carl-Johan H. Seger, Randal E. Bryant: Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories. Formal Methods in System Design 6(2): 147-189 (1995)
21	EE	Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger: Automatic Verification of Asynchronous Circuits. IEEE Design & Test of Computers 12(1): 24-31 (1995)
20	EE	Scott Hazelhurst, Carl-Johan H. Seger: A simple theorem prover based on symbolic trajectory evaluation and BDD's. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 413-422 (1995)
1994
19		Jeffrey J. Joyce, Carl-Johan H. Seger: Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG '93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings Springer 1994
18		Scott Hazelhurst, Carl-Johan H. Seger: Composing Symbolic Trajectory Evaluation Results. CAV 1994: 273-285
17		Zheng Zhu, Carl-Johan H. Seger: The Completeness of a Hardware Inference System. CAV 1994: 286-298
16		Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger: Automatic Verification of Refinement. ICCD 1994: 225-229
15		Carl-Johan H. Seger, Randal E. Bryant: Digital Circuit Verification Using Partially-Ordered State Models. ISMVL 1994: 2-7
14		Carl-Johan H. Seger, Janusz A. Brzozowski: Generalized Ternary Simulation of Sequential Circuits. ITA 28(3-4): 159-186 (1994)
1993
13	EE	Jeffrey J. Joyce, Carl-Johan H. Seger: Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. DAC 1993: 469-474
12		Jeffrey J. Joyce, Carl-Johan H. Seger: The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover. HUG 1993: 185-198
11		Zheng Zhu, Jeffrey J. Joyce, Carl-Johan H. Seger: Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment. HUG 1993: 253-266
10		Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger: From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation. HUG 1993: 489-500
1991
9		Carl-Johan H. Seger, Jeffrey J. Joyce: A Two-Level Formal Verification Methodology using HOL and COSMOS. CAV 1991: 299-309
8	EE	Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger: Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation. DAC 1991: 397-402
7		Carl-Johan H. Seger: On the Existence of Speed-Independent Circuits. Theor. Comput. Sci. 86(2): 343-364 (1991)
1990
6		Randal E. Bryant, Carl-Johan H. Seger: Formal Verification of Digital Circuits Using Symbolic Ternary System Models. CAV 1990: 33-43
1989
5	EE	Janusz A. Brzozowski, Carl-Johan H. Seger: A unified framework for race analysis of asynchronous networks. J. ACM 36(1): 20-45 (1989)
1988
4		Carl-Johan H. Seger, Janusz A. Brzozowski: An Optimistic Ternary Simulation of Gate Races. Theor. Comput. Sci. 61: 49-66 (1988)
1987
3		Janusz A. Brzozowski, Carl-Johan H. Seger: A Characterization of Ternary Simulation of Gate Networks. IEEE Trans. Computers 36(11): 1318-1327 (1987)
1986
2		Janusz A. Brzozowski, Carl-Johan H. Seger: Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary). ICALP 1986: 69-78
1		David J. Taylor, Carl-Johan H. Seger: Robust Storage Structures for Crash Recovery. IEEE Trans. Computers 35(4): 288-295 (1986)

Coauthor Index

1	Mark Aagaard	[23] [28] [30] [31] [33] [34] [36] [42]
2	Sara Adams	[43]
3	Clark W. Barrett (Clark Barrett)	[42]
4	Derek L. Beatty	[8]
5	Magnus Björk	[43]
6	Randal E. Bryant	[6] [8] [15] [22]
7	Janusz A. Brzozowski	[2] [3] [4] [5] [14]
8	David L. Dill	[24]
9	Mark R. Greenstreet	[16] [21]
10	Ziyad Hanna	[38]
11	Scott Hazelhurst	[18] [20] [25] [29]
12	Robert B. Jones	[24] [28] [30] [31] [33] [34] [36] [42]
13	Jeffrey J. Joyce	[9] [10] [11] [12] [13] [19]
14	Daher Kaiss	[38]
15	Roope Kaivola	[34]
16	Katherine R. Kohatsu	[34]
17	Trevor Wing Sang Lee	[16] [21]
18	Thomas F. Melham	[33] [36] [42] [43]
19	John Moondanos	[38]
20	John W. O'Leary	[33] [36] [42]
21	Sreeranga P. Rajan	[10]
22	Don Syme	[42]
23	David J. Taylor	[1]
24	Jin Yang	[37] [39] [40] [41]
25	Zheng Zhu	[11] [17]

Colors in the list of coauthors