| 2001 |
|---|
| 21 | EE | Chih-Yang Hsu,
Chaur-Wen Wei,
Wen-Zen Shen:
A pattern compaction technique for power estimation based on power sensitivity information.
ISCAS (5) 2001: 467-470 |
| 20 | EE | Heng-Liang Huang,
Yeong-Ren Chen,
Jing-Yang Jou,
Wen-Zen Shen:
Grouped input power sensitive transition an input sequence compaction technique for power estimation.
ISCAS (5) 2001: 471-474 |
| 2000 |
|---|
| 19 | EE | Heng-Liang Huang,
Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A new method for constructing IP level power model based on power sensitivity.
ASP-DAC 2000: 135-140 |
| 18 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. VLSI Syst. 8(4): 392-400 (2000) |
| 1999 |
|---|
| 17 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A structure-oriented power modeling technique for macrocells.
IEEE Trans. VLSI Syst. 7(3): 380-391 (1999) |
| 1998 |
|---|
| 16 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen,
Hsien-Ho Chuang:
On circuit clustering for area/delay tradeoff under capacity and pin constraints.
IEEE Trans. VLSI Syst. 6(4): 634-642 (1998) |
| 1997 |
|---|
| 15 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A power modeling and characterization method for macrocells using structure information.
ICCAD 1997: 502-506 |
| 1996 |
|---|
| 14 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
ICCAD 1996: 13-17 |
| 13 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A power modeling and characterization method for the CMOS standard cell library.
ICCAD 1996: 400-404 |
| 1995 |
|---|
| 12 | EE | Wen-Zen Shen,
Jiing-Yuan Lin,
Fong-Wen Wang:
Transistor reordering rules for power reduction in CMOS gates.
ASP-DAC 1995 |
| 11 | EE | Jwu E. Chen,
Chung-Len Lee,
Wen-Zen Shen,
Beyin Chen:
Fanout fault analysis for digital logic circuits.
Asian Test Symposium 1995: 33-39 |
| 10 | EE | Wen-Zen Shen,
Juinn-Dar Huang,
Shih-Min Chao:
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping.
DAC 1995: 65-69 |
| 9 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
ICCAD 1995: 359-363 |
| 1994 |
|---|
| 8 | EE | Jiing-Yuan Lin,
Tai-Chien Liu,
Wen-Zen Shen:
A cell-based power estimation in CMOS combinational circuits.
ICCAD 1994: 304-309 |
| 7 | | Wen-Zen Shen,
Yi-Hsin Tao,
Lan-Rong Dung:
On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design.
ISCAS 1994: 171-174 |
| 1993 |
|---|
| 6 | | Wen-Zen Shen,
Gwo-Haur Hwang,
Wen-Jun Hsu,
Yun-Jung Jan:
Design of Pseudoexhaustive Testable PLA with Low Overhead.
IEEE Trans. Computers 42(7): 887-891 (1993) |
| 1992 |
|---|
| 5 | EE | Wen-Jun Hsu,
Wen-Zen Shen:
Coalgebraic Division for Multilevel Logic Synthesis.
DAC 1992: 438-442 |
| 4 | EE | Chung-Len Lee,
Ching Ping Wu,
Wen-Zen Shen,
Tyh-Song Hwang,
Shueng Dar Hwang:
MT-SIM a mixed-level transition fault simulator based on parallel patterns.
J. Electronic Testing 3(1): 67-78 (1992) |
| 1991 |
|---|
| 3 | EE | Jwu E. Chen,
Chung-Len Lee,
Wen-Zen Shen:
Single-fault fault-collapsing analysis in sequential logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1559-1568 (1991) |
| 2 | EE | Jwu E. Chen,
Chung-Len Lee,
Wen-Zen Shen:
Checkpoints in irredundant two-level combinational circuits.
J. Electronic Testing 2(4): 395-397 (1991) |
| 1990 |
|---|
| 1 | EE | Tyh-Song Hwang,
Chung-Len Lee,
Wen-Zen Shen,
Ching Ping Wu:
A Parallel Pattern Mixed-Level Fault Simulator.
DAC 1990: 716-719 |
